Browsing by Author "Ma, RL"

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Instruction folding in Java processor
(1997)
Ton, LR
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Chang, LC
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Rao, MF
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Tseng, HM
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Shang, SS
Traditionally, the performance of a stack machine was limited by the true data dependency. A performance enhancement mechanism - Stack Operations Folding - was used in Srm Microelectronics' picoJava design [1][2] and it can reduce up to 60% of all stack operations. in this paper, we use the Java bytecode language as the targe; machine language, and study its instruction folding on a proposed machine model. Three folding strategies: 2-foldable, 3-foldable and 4-foldable, were simulated and evaluated. Statistical data show that our third folding strategy eliminates 73% of all stack operations, and each strategy fins an overall program speedup of 1.19, 1.25 and 1.26, respectively, as compared to a traditional stack machine. Moreover, a Java machine model suitable for instruction folding, together with its pipeline stages, are presented. lt seems to have the best cost/performance effectiveness of a Java stack machine if six bytes decoder width and the second folding strategy - the three-foldable strategy - are adopted.
Periodic adaptive branch prediction and its application in superscalar processing in Prolog
(1995)
Ma, RL
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Chung, CP
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交大名義發表
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資訊工程學系
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National Chiao Tung University
Branch instructions create barriers to instruction prefetching, greatly reducing the fine-grained parallelism of programs. Branch prediction is a common method for solving this problem. We first present four lemmata in this paper describing the relationships among branch prediction hit rate and system performance, hardware efficiency, and branch prediction overhead. We then propose a branch prediction method called PAM (Periodic Adaptive Method). An abstract model and detailed implementation of PAM are described. PAM's prediction hit rate as measured by 10 Prolog benchmark programs is 97%. When implemented in a superscalar Prolog system, PAM enhances the degree of system parallelism by 68.8%. PAM can be applied to languages and applications other then the Prolog system we used in this study.
Reducing memory traffic and accelerating prolog execution in a superscalar prolog system
(1999-11-01)
Ma, RL
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Chung, CP
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資訊科學與工程研究所
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Institute of Computer Science and Engineering
Memory access operations constitute about 32.7% of all the operations executed in a typical Prolog program. Among these memory accesses, 75% are to the program control structures (environments and choice points). These memory accesses plus possible data cache misses greatly impair system performance, and the problem is even more severe in a VLIW, superscalar, or superpipelined Prolog system. This paper describes an innovative windowed register file management technique called SORWT (splittable overlapping register window technique). With SORWT, environments, choice points, and arguments can be stored in a windowed register file. SORWT reduces the number of memory accesses to only 25% of the number made when a conventional stack scheme is used. This paper describes in detail how Warren and PLM instructions can be implemented using SORWT and it presents a register file overflow/underflow handling mechanism called the memory window matrix (MWM) and a mapping function for use between register windows and the MWM. Thirty benchmark programs are used to study performance issues, the overhead of SORWT, optimal register file and window sizes, and the argument overflow rate.