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Browsing by Author "Ma, Yu-Sheng"

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    A Fully Integrated Asymmetrical Shunt Switched-Capacitor DC-DC Converter With Fast Optimum Ratio Searching Scheme for Load Transient Enhancement
    (2019-09-01)
    Lin, Yen-Ting
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    Lai, Yan-Jiun
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    Chen, Hung-Wei
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    Yang, Wen-Hau
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    Ma, Yu-Sheng
    This paper presents a modified negator-based switched-capacitor (NSC) dc-dc converter to achieve fine-grained voltage conversion ratios. Based on a concept of reconfiguring several 2: 1 switched-capacitor (SC) converters in series and parallel at the last stage, the proposed asymmetrical shunt SC (ASSC) converter provides more controllable variables of forward gain and feedback gain to decide different power path interconnections and increase the available conversion ratios, with a little sacrifice of its slow switching limit output impedance. The switching loss of the bottom-plate parasitic capacitance in the ASSC converter is less than the switching loss of the NSC topology because the two moderate voltages instead of the power rail are fed to the last stage 2: 1 SC unit and reduce the voltage swing. The bottom-plate swapping prototype further reduces the parasitic loss at high conversion ratios. To handle a large number of conversion ratios in closed-loop regulation, the ASSC converter uses the fast optimum ratio searching (FORS) technique, which evaluates the transient voltage drop to quickly search for target ratios and reduce the transient recovery time. A three-stage ASSC converter achieving 187 conversion ratios is fully integrated in the test chip, which is fabricated in 0.25-mu m CMOS process with an active area of 7.14 mm(2). Furthermore, 2389 conversion ratios can be derived in theory for a four-stage ASSC converter. The proposed reconfigurable SC converter provides an output voltage range of 0.4 to 2.8 V under no load conditions, and greater than 80% power efficiency at an output voltage level of 0.9 to 1.5 V over a load range of 3 to 9.5 mA. Due to the FORS technique, the measured transient recovery time is reduced from 7 to 1.5 mu s in case of load current step of 7 mA.
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    A High Efficiency and Fast Transient Digital Low-Dropout Assisted Switched-Capacitor Converter for EMI-Free Internet of Everything (IoE) Systems
    (2017-01-01)
    Chen, Shao-Qi
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    Lin, Yen-Ting
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    Ma, Yu-Sheng
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    Yang, Wen-Hau
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    Chen, Ke-Horng
    State-of-the-art closed-loop switched-capacitor (SC) designs usually regulate the output voltage by pulse frequency modulation (PFM) with the disadvantage of large electromagnetic interference (EMI). It may cause the failure of the Internet of Everything (IoE) devices. This paper proposes the hybrid digital low drop-out (DLDO) SC converter with a constant switching pulse width modulation (PWM) control for low EMI. Besides, the analog-to-digital current conversion provided by the DLDO due to its fast transient response can predict the desired ratio for the SC and reduce the dip voltage at the same time. The handshaking technique achieves smooth transition in the hybrid architecture. Experimental results show peak efficiency of 85% (closed-loop) and 95% (open loop) since the power converter has fast transient response by the DLDO prediction and reduction of switching power loss. Accurate fine tune operation by the DLDO and smooth handshaking improve load regulation from 49mV to 3mV and undershoot from 263mV to 93mV with a reduced recovery time of 200ns.
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    A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
    (2020-04-01)
    Lin, Jian-He
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    Yang, Shang-Hsien
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    Muniandi, Balakumar
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    Ma, Yu-Sheng
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    Huang, Chia-Ming
    The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 A and reduces the switching power loss through variable switching frequency control. With a load step of 1-20mA, the transient response time is 1.3 s and the peak current efficiency is 99.8 at heavy loads.
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    A Low Quiescent Current and Cross Regulation Single-Inductor Dual-Output Converter with Stacking MOSFET Driving Technique
    (2017-01-01)
    Ma, Yu-Sheng
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    Yang, Wen-Hau
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    Lin, Yen-Ting
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    Chen, Hsin
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    Lin, Li-Chi
    the stacking MOSFET structure composed of low-voltage devices suffers from deteriorated transient response or large footprint area when capacitor-free or dominant pole compensation low dropout (LDO) regulator biases the driver. Due to self-stabilized feature, the proposed stacking MOSFET driving (SMD) technique effectively drives the power stage and greatly reduces noise interference from the noisy node to achieve low cross regulation (CR) in the single-inductor dual-output (SIDO) converter. Moreover, two inherent low dropout (LDO) regulators in the SMD technique completely regulate two outputs with low quiescent current at no load condition. Experimental results show the tested chip fabricated in 0.25 mu m process with low cross regulation of 0.015mV/mA and ultra-low quiescent current of 5 mu A at no load condition.
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    A Single-Inductor Dual-Output Converter With the Stacked MOSFET Driving Technique for Low Quiescent Current and Cross Regulation
    (2019-03-01)
    Chen, Hsin
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    Huang, Chao-Jen
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    Kuo, Chun-Chieh
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    Lin, Li-Chi
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    Ma, Yu-Sheng
    Stacked MOSFET structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked MOSFET driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-mu m process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 mu A under no-load conditions.
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    A True-Random-Number-Based Pseudohysteresis Controller for Buck DC-DC Converter in High-Security Internet-of-Everything Devices
    (2020-03-01)
    Yang, Wen-Hau
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    Chiu, Shao-Wei
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    Kuo, Chun-Chieh
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    Lin, Yen-Ting
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    Lai, Yan-Jiun
    For high-security Internet-of-Everything (IoE) devices, a true random number (TRN)-based pseudohysteresis controller (PHC) is proposed to avoid both power side-channel attack (PSCA) and power injection attack (PIA) and reduce electromagnetic interference (EMI) without degrading performance of transient response and regulation. In addition, the TRN-based PHC uses an enhanced security randomizer to correctly generate a random number (RN) independent of the input power at the PSCA and PIA and converts the RN into a hysteresis window that constitutes the true random modulation switching frequency. Therefore, the TRN-based PHC ensures proper spread spectrum and low EMI. In addition, fast transient response is maintained due to inherent hysteresis control. Experimental results show that peak EMI noise is reduced from 89.72 to 54.32dBV and meets the specification of EN 55032 Class B even under the PIA interference up to 1 V. Furthermore, in case of 0.2A-to-0.8A load step, the method achieves a recovery time of 7.3 s and an output voltage drop of 53 mV at a switching frequency of approximately 1 MHz, and the peak efficiency is 92.4.
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    Unsymmetrical Parallel Switched-Capacitor (UP-SC) Regulator with Fast Searching Optimum Ratio Technique
    (2017-01-01)
    Lin, Yen-Ting
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    Yang, Wen-Hau
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    Ma, Yu-Sheng
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    Lai, Yan-Jiun
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    Chen, Hung-Wei
    Different from conventional multiphase switched-capacitor (SC) DC-DC converters, the proposed unsymmetrical parallel switched-capacitor (UP-SC) regulator provides more controllable input variables to increase available conversion ratios for improved load regulation. Even under higher conversion ratio numbers, the UP-SC regulator uses the fast searching optimum ratio (FSOR) technique to search the destined ratio rapidly and to reduce the transient recovery time. Experimental results show the test chip fabricated in 0.25 mu m CMOS process increases the ratio number to 187 and 2389 in 3-stage and 4-stage SC regulators, respectively. Transient recovery time reduces from 26 mu s to 1.5 mu s in case of 7mA load current step.