Browsing by Author "Markovic, Dejan"

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A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
(2012-09-01)
Yu, Tsung-Han
;
Yang, Chia-Hsiang
;
Cabric, Danijela
;
Markovic, Dejan
;
電子工程學系及電子研究所
"A digital baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm in 65-nm(2) CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability >= 0.9 and false-alarm probability <= 0.1 for -5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22x reduction in power per sensing bandwidth compared with prior work."
A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection
(2011-01-01)
Yuan, Fang-Li
;
Yang, Chia-Hsiang
;
Markovic, Dejan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a hybrid soft-output MIMO detector that searches reliable soft-information in both deterministic and probabilistic ways. The fixed-complexity sphere detector (FSD) is first applied to provide near maximum-likelihood (ML) solutions. The solutions are next used to initialize the Markov Chain Monte Carlo (MCMC) detector that uses parallel Gibbs samplers (GSs) for remaining candidate enumeration. A lowcomplexity VLSI architecture is proposed to demonstrate the feasibility of hardware realization for high-throughput applications. Simulation results indicate that the hybrid detector has a 2.3x complexity reduction and a 2x throughput improvement compared to individual soft-output FSD and MCMC detectors.
An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing
(2011)
Yu, Tsung-Han
;
Yang, Chia-Hsiang
;
Markovic, Dejan
;
Cabric, Danijela
;
電子工程學系及電子研究所
Spectrum sensing over a wide bandwidth increases the probability of finding unutilized spectrum for cognitive radios. However, energy-efficient VLSI realization of wideband sensing algorithms is challenging due to complex signal processing and real-time requirement. In addition, strong primary users introduce spectral leakage in adjacent unused bands, resulting in sensing performance degradation. To address these challenges, we propose a cascaded filter-bank channelization scheme and its re-configurable VLSI architecture that can be optimized for power, area, sensing time, and detection performance. In addition, the spectral leakage due to strong interference is compensated with an interference cancellation method. Compared to the conventional PSD-based energy detection, the proposed channelization scheme supports reliable wideband signal detection with 2.5x less power. Given a 0.5ms sensing time under 30-dB adjacent-band interference-to-noise ratio, a 30x sensing-time improvement is achieved while maintaining a false-alarm probability of 0.1 and a detection probability of 0.9. The energy efficiency is improved from lower power consumption and reduced sensing time.
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example
(2012-03-01)
Yang, Chia-Hsiang
;
Yu, Tsung-Han
;
Markovic, Dejan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a design methodology for power and area minimization of flexible FFT processors. The methodology is based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables. Radix factorization is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. As a proof of concept, a 128- to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process. The processor designed for minimum power-area product is integrated in 1.25 x 1.1 mm(2) and dissipates 4.05 mW at 0.45 V for the 20 MHz LTE bandwidth. The energy dissipation ranging from 2.5 to 103.7 nJ/FFT for 128 to 2048 points makes it the lowest energy flexible FFT.