Browsing by Author "Meng, Chin-Chun"

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2.4-GHz 7.4-mW 300-kHz Flicker-Noise-Corner Direct Conversion Receiver Using 0.18 mu m CMOS and Deep-N-Well NPN BJT
(2013)
Chang, Wei-Ling
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Meng, Chin-Chun
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Syu, Jin-Siang
;
Wang, Chia-Ling
;
Huang, Guo-Wei
A low-power low-flicker-noise receiver is demonstrated using 0.18 mu m CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.
2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver-Hartley Image-Rejection Techniques
(2009-03-01)
Meng, Chin-Chun
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Wu, Tzung-Han
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Syu, Jin-Siang
;
Yu, Sheng-Wen
;
Tsung, Kuan-Chang
A 2.4/5.7-GHz dual-band Weaver-Hartley architecture, using 0.18-mu m CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver-Hartley architecture.
9.9-mA 5-6 GHz CMOS Sub-Harmonic Direct-Conversion Receiver Using Deep N-Well BJT
(2014-01-01)
Chang, Wei-Ling
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Meng, Chin-Chun
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Syu, Jin-Siang
;
Wang, Chia-Ling
;
Huang, Guo-Wei
A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 mu m CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.
A 5 GHz RFIC single chip solution in GaInP/GaAs HBT technology
(2008-02-01)
Meng, Chin-Chun
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Wu, Tzung-Han
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電信工程研究所
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Institute of Communications Engineering
Several high performance GaInP/GaAs heterojunction bipolar transistor (HBT) radio frequency integrated circuits (RFIC) implemented by our research group are reviewed in this article. These demonstrated RFICs include source inductively degenerated cascode low noise amplifiers with inter-stage matching, shunt-series shunt-shunt dual-feedback wideband amplifiers, a broadband Gilbert down-conversion micromixer, Gilbert down-conversion mixers with polyphase filters for image rejection, a dual-conversion Weaver receiver, Gilbert up-conversion mixers with output LC current mirror and quadrature VCOs.
Analysis and Design of the 0.13-mu m CMOS Shunt-Series Series-Shunt Dual-Feedback Amplifier
(2009-11-01)
Wu, Tzung-Han
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Syu, Jin-Siang
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Meng, Chin-Chun
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電子工程學系及電子研究所
;
電信工程研究所
This paper demonstrates the design methodology of the shunt-series series-shunt dual-feedback Meyer wideband amplifier. The small-signal S-parameters are obtained for the first time using the pole-and-zero analysis, thus giving the RF designers a detailed insight into the Meyer amplifier. A 10-GHz wideband amplifier is demonstrated in this paper, using 0.13-mu m CMOS technology to verify our design theory. The experimental results of the S-parameters highly agree with our theory.
GaInP/GaAs HBT sub-harmonic Gilbert mixers using stacked-LO and leveled-LO topologies
(2007-05-01)
Wu, Tzung-Han
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Tseng, Sheng-Che
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Meng, Chin-Chun
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Huang, Guo-Wei
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電信工程研究所
This paper discusses and demonstrates the most popular sub-harmonic Gilbert mixers in 2-mu m GaInP/GaAs HBT technology. High two local oscillators (2LO)-to-RF isolation is important to alleviate the self-mixing problem of the sub-harmonic mixer. The demonstrated GaInP/GaAs HBT stacked-local oscillator (LO) mixer topology has achieved the best 2LO-to-RF isolation when compared with the previous literature. On the other hand, the leveled-LO sub-harmonic mixers have advantages in terms of the high speed and low dc supply voltage at the cost of much larger LO pumping power. Among all the structures, the bottom-LO sub-harmonic mixer has the lowest current consumption and the simplest circuit structure at the expense of the 2LO-to-RF isolation.
Large Improvement in Image Rejection of Double-Quadrature Dual-Conversion Low-IF Architectures
(2010-07-01)
Syu, Jin-Siang
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Meng, Chin-Chun
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Teng, Ya-Hui
;
Liao, Hua-Yu
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電機工程學系
The reasons for a degradation of image-rejection performance in double-quadrature-double-quadrature and single-quadrature-double-quadrature dual-conversion low-IF downconverters are fully discussed in this paper. Polyphase filters (PPFs) are inserted at proper positions to minimize the effects of device/signal mismatches, and thus improve the image rejection without calibration. Both a 0.35-mu m SiGe heterojunction bipolar transistor 5.2-GHz double-quadrature-double-quadrature downconverter with an RF PPF and a 0.18-mu m CMOS 2.2/4.8-GHz single-quadrature-double-quadrature downconverter with a switched-band low-noise amplifier (LNA) and a narrowband inter-stage PPF are demonstrated. Compared with our previous work, the 5.2-GHz downconverter achieves a 15-dB improvement in image-rejection ratio (IRR) of the first image signal (IRRR(1)) even without a pre-selection filter or LNA. Additionally, the dual-band downconverter has a 25-dB improvement in IRR of the second image signal (IRRR(2)), which nearly reaches the theoretical limit of a four-stage PPF covering 20-40 MHz.