Browsing by Author "Meng, Chinchun"

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0.13-mu M CMOS Q-BAND LEVELED-LO SUBHARMONIC MIXER WITH INJECTION-LOCKED FREQUENCY-DIVIDER QUADRATURE GENERATOR
(2009-11-01)
Su, Jen-Yi
;
Meng, Chinchun
;
Wu, Po-Yi
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
In this article, a 40-GHz subharmonic Gilbert down-conversion mixer with an accurate quadrature local oscillator (LO) input is demonstrated using a standard 0.13-mu m CMOS technology. The quadrature-output frequency divider is realized by injection-locked oscillators and is used at the LO port to replace conventional RC-CR polyphase filters at higher frequencies. Furthermore, the proper Marchand balun at all RF stage is suitable for the standard Si-based process to generate precisely balanced signals despite the substrate loss. The measured conversion gat In is 4 dB at 40 GHz. The IP(1dB) IIP(3) of - 7 dBm and 2 dBm, respectively, tire achieved. The measured 3-dB RF bandwidth is very broad and about 12-GHz bandwidth when the 10-MHz IF frequency is fixed. The die Size is about I mm X I mm. (C) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2663-2665, 2009; Published online in Wiley InterScience (www.interscience.wiley.com), DOI 10.1002/mop.24714
0.18 mu m SiGe BiCMOS Microwave/Millimeter-wave Dual-Mode Dual-Conversion Receiver Architecture With a Tunable RF Channel Selection at Low-Flicker-Noise Microwave Mode
(2017-01-01)
Chang, Wei Ling
;
Meng, Chinchun
;
Yang, Shih-Der
;
Huang, Guo-Wei
;
電機工程學系
A dual-mode receiver architecture with tens-MHz channel bandwidth at microwave mode and GHz channel bandwidth at millimeter-wave mode is demonstrated in this work with a tunable active filter for RF channel selection at microwave mode using 0.18 mu m SiGe BiCMOS technology. A dual conversion is employed to accommodate the wide-channel-bandwidth 60-GHz mode at the first conversion stage and the high-level-modulation 5-GHz mode is merged to the second conversion stage through sharing the 5-GHz switchable Gilbert IQ mixers with the 60-GHz mode. A tunable RF active filter is inserted between the 5-GHz LNA and the second stage mixer to serve as RF channel selection at the 5-GHz mode with the ability of relaxing the stringent linearity requirement imposed by high-level-modulation scheme. 10 dB gain with a 2-GHz channel bandwidth at the 60-GHz mode and 23 dB gain with a 20 MHz channel bandwidth within the 600 MHz tuning range at 5-GHz mode are demonstrated with a low-flicker-noise corner of less than 60 KHz at the 5-GHz mode because of the use of SiGe HBT as the IQ Gilbert mixer cores at the second conversion stage.
10-GHz highly symmetrical sub-harmonic Gilbert mixer using GaInP/GaAs HBT technology
(2007-05-01)
Wu, Tzung-Han
;
Meng, Chinchun
;
電信工程研究所
;
Institute of Communications Engineering
A 10-GHz sub-harmonic Gilbert mixer is demonstrated using GaInP/GaAs hetero-junction bipolar transistor technology. The local oscillator (LO) signal time-delay path in the sub-harmonic LO stage is compensated using the fully symmetrical stacked-LO doubler; therefore, the balance of the sub-harmonic LO stage, the radio frequency to intermediate frequency isolation, and IIP2 are improved. The demonstrated 10-GHz sub-harmonic mixer achieves 10 dB conversion gain, IP1dB of -12 dBm, IIP3 of 2 dBm and IIP2 of 33 dBm.
10-GHz SiGeBiCMOS sub-harmonic Gilbert mixer using the fully symmetrical and time-delay compensated LO cells
(2007-02-01)
Wu, Tzung-Han
;
Meng, Chinchun
;
電信工程研究所
;
Institute of Communications Engineering
A 10-GHz sub-harmonic Gilbert mixer is demonstrated in this paper using the 0.35 mu m SiGe BiCMOS technology. The time-delay when the sub-harmonic LO (Local Oscillator) stage generates subharmonic LO signals is compensated by using fully symmetrical multiplier pairs. High RF-to-IF isolation and sub-harmonic LO Gilbert cell with excellent frequency response can be achieved by the elimination of the time-delay. The SiGe BiCMOS sub-harmonic micromixer exhibits 17 dB conversion gain, -74 dB 2LO-to-RF isolation, IP1dB of -20 dBm, and IIP3 Of -10 dBm. The measured double sideband noise figure is 16 dB from 100-kHz to 100-MHz because the SiGe bipolar device has very low 1/f noise corner.
11.8 GHz GaInP/GaAs HBT dynamic frequency divider using HLO-FF technique
(2008-10-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Chang, YuWen
;
Huang, Guo-Wei
;
電信工程研究所
An integrated GaInP/GaAs heterojunction bipolar transistor (HBT) dynamic frequency divider based on HLO-FF (high-speed latching operating flip-flop) structure is demonstrated rot 4.1-11.8 GHz. In this experiment, et conventional static,frequency divider using the same cut-off-frequency device is also fabricated for comparison. By biasing the HBT transistors around the peak of f(T) and optimizing the I(read)/I(latch) tire maximum operating frequency of the HLO-FF is greatly improved date to higher slew-rate and smaller voltage swing. The speed of HLO-FF is faster about 48% than that of static structure. The core current is 13 mA cot the supply voltage of 5V. (C) 2005 Wiley Periodicals, Inc.
12 similar to 18 GHz Resistive Mixer with a Miniature Marchand Balun using Standard CMOS Process
(2009)
Wei, Hung-Ju
;
Meng, Chinchun
;
Tsung, Kuan-Chang
;
Huang, Guo-Wei
;
電信工程研究所
A 12 similar to 18 GHz fundamental resistive mixer is demonstrated using standard 0.13 mu m CMOS technology. A Marchand Balun directly on lossy silicon substrate is integrated with the resistive mixer to generate equal-amplitude and out-of-phase signal for LO pumping. The size of the Ku-band Marchand balun only occupies 478 mu m x 250 mu m due to higher silicon dielectric constant. The measured conversion loss of the resistive mixer is around 22 dB under f(IF)=3 GHz and P(LO)=6 dBm. The small required LO power reveals that the Marchand balun does not suffer serious loss from silicon substrate. The miniature technique makes passive components more compact and easier to be integrated with IC circuit design.
15 GHz High-Isolation Sub-Harmonic Mixer With Delay Compensation
(2009-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-GHz high-isolation sub-harmonic mixer (SHM) with delay compensation is demonstrated in this letter using 0.35 mu m SiGe heterojunction bipolar transistor (HBT) technology. The proposed SHM consisting of two parallel stacked-LO mixer cores with opposite LO I/Q inputs substantially improves port-to-port isolation. A mathematical analysis regarding the isolation properties is also included in this letter. Further, a conventional stacked-LO SHM (w/o compensation) is also implemented with the same device sizes and bias conditions for a fair comparison. SHMs w/ and w/o compensation have similar conversion gain of 9/10 dB and noise figure of 14/13.5 dB when f(LO) = 7.5 GHz. However, the delay compensation technique improves the 2LO-RF/IF isolation by 34/35 dB, the LO-RF/IF isolation by 8/9 dB, and the RF-IF isolation by 22 dB.
15 GHz Wideband CMOS Gilbert Up-Converter With Stacked Spiral-CPS Phase-Inverter Rat-Race Coupler at RF Port
(2013)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Wu, Po-Yi
;
Huang, Guo-wei
;
電機資訊學士班
A miniaturized phase-inverter rat-race and its wideband Gilbert up-converter is demonstrated in 0.13-mu m CMOS technology. The common-mode LO leakage can be absorbed by the isolated port of the rat-race coupler while the rate-race employed at RF port to combine the mixer differential output. A phase-inverter rat-race coupler with a stacked spiral-shape coplanar stripline (CPS) by multi-layer metals can highly reduce the chip size. Finally, the experimental results of up-converter shows the 1-dB conversion gain and 15 GHz RF bandwidth. The IF-to-RF isolation is about 50 dB and LO-to-RF isolation is about 23 dB, respectively.
16-GHz mHEMT Double-Quadrature Gilbert Down-Conversion Mixer With Polyphase Filters
(2013)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 16-GHz double-quadrature very low IF down conversion mixer with polyphase filters is demonstrated using 0.15-nm metamorphic high electron mobility transistor (mHEMT) technology. Due to the hgih cut-off frequency of mHEMT device, the image rejection Gilbert mixer works at 16 GHz. The polyphase filters are employed to generate differential quadrature signals and eliminate the image signal at RF/LO stages and IF stage, respectively, in the double quarture configuration. When RF and LO frequencies are designed around 16 GHz and an IF frequency is 32 MHz, The double-quadrature Gilbert down-converter has 32-dB image rejection ratio, 1.7-dB conversion gain, -5-dBm IP1dB, and 5-dBm IIP3. The die size is 3.0 mm x 3.2 mm.
16.4 GHz SiGe BiCMOS Sub-Harmonic Mixer With Reactive I/Q Generators in RF and LO Paths
(2009)
Tseng, Sheng-Che
;
Syu, Jin-Siang
;
Su, Jen-Yi
;
Wei, Hung-Ju
;
Meng, Chinchun
This paper demonstrates a high-frequency 0.35-mu m SiGe BiCMOS sub-harmonic downconverter with reactive in-phase and quadrature-phase (I/Q) generators. Two reactive I/Q generators are integrated in our work to provide differential quadrature RI and LO signals. The I/Q sub-harmonic downconverter with single-ended LO, RI, and IF (IM) ports has a conversion gain of 1 dB, IP(1dB) of -10 dBm, IIP(3) of 0 dBm and IIP(2) of 21 dBm at 16.4 GHz. The magnitude and phase errors between the I and Q channels are 1.34% and 0.6 degrees, respectively. The dc power consumption of this I/Q mixer without output buffers is approximately 5 mW.
17-GHz pHEMT Gilbert Single-Quadrature Downconverter With Polyphase Filters for Image Rejection
(2010-01-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 17-GHz Gilbert single-quadrature down-converter (SQDC) with polyphase filters is successfully demonstrated using 0.15-mu m pseudomorphic high electron mobility transistor (pHEMT) technology for the first time to the best of our knowledge. Thanks to the semi-insulating GaAs substrate and an advanced technology, the image rejection Gilbert mixer works well at high frequencies. A polyphase filter at the LO stage is employed to generate precisely differential quadrature signals and a four-stage polyphase filter at the IF stage can filter out the unwanted image signal to achieve image rejection. From 10-MHz to 90-MHz IF frequencies, a 30-dB image rejection ratio is achieved when RF and LO frequencies are designed around 17 GHz. The Gilbert SQDC has a 5.5-dB conversion gain, 0-dBm IP1db, and 16-dBm IIP3.
2-GHz 1.35-dB NF pHEMT Single-Voltage-Supply Process-Independent Low-Noise Amplifier
(2018-01-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yang, Chun
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
A 2-GHz single-voltage-supply 0.15-mu m depletion-mode (D-mode) pseudomorphic high electron-mobility transistor (pHEMT) low-noise amplifier (LNA) is demonstrated with a proposed process-independent self-biasing scheme. The current-reused technique is also employed to achieve a common-source common-drain two-stage LNA under a dc current of 10.85 mA at a 3-V supply. As a result, the proposed LNA achieves 20-dB power gain and 1.35-dB noise figure (NF) at 2 GHz while the minimum NF=1.3 dB occurs at 2.4 GHz.
.2.4 GHz divide-by-256 similar to 271 single-ended frequency divider in standard 0.35-mu m CMOS technology
(2005)
Tseng, Sheng-Che
;
Meng, Chinchun
;
Li, Shao-Yu
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Su, Jen-Yi
;
Huang, Guo-Wei
This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-um 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.20.7 mm(2).
2.4-GHz Low-Noise Direct-Conversion Receiver With Deep N-Well Vertical-NPN BJT Operating Near Cutoff Frequency
(2011-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-mu m CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency (f(T)) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor f(T), the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has conversion gain of 51 dB and noise figure of 3.2 dB with 70-kHz 1/f noise corner, while the current consumption is 4.5 mA at a 1.8-V supply.
2.4-GHz Q-Enhanced Lumped Ring Filter With Two Transmission Zeros Using 0.18-mu m SiGe BiCMOS Process
(2017-03-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Yang, Shih-Te
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電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz Q-enhanced lumped ring filter with a narrow bandpass response and two stopband-rejection transmission zeros using 0.18-mu m SiGe BiCMOS technology is demonstrated in this letter. A transformer-based Q-enhanced technique is employed to boost the Q-factor of on-chip inductors for low passband insertion loss. The measured results show zero dB insertion loss, 120-MHz 3-dB bandwidth for the passband centered at 2.45 GHz and with two transmission zeros at 2.35 and 2.65 GHz, respectively. The noise figure is about 14.5 dB, IP1dB is about -15.2 dBm and IIP3 is about -4.5 dBm, respectively. The total current consumption is 9.9 mA at 1.8 V supply voltage.
2.4-GHz Tunable Miniature CMOS Active Bandpass Filter With Two Transmission Zeros Using Lumped Stepped-Impedance Ring Resonator
(2018-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Chien, Hsieh-Hsiu Chang
;
Huang, Guo-Wei
;
電機工程學系
This paper demonstrates a small-size 2.4-GHz CMOS active bandpass filter with two transmission zeros using a lumped stepped-impedance ring resonator. To obtain low insertion loss and small size, four high-Q active inductors using 0.18 gm CMOS transistors only are employed in the design. The measured insertion loss is 2.9-dB at 2.4 GHz center frequency with two transmission zeros located at 2.1 GHz and 3.1 GHz, respectively. By tuning the bias currents of active inductors, the center frequency has 1.4 GHz tuning range and the 1-dB bandwidth can be adjusted in the range of 190 MHz to 260 MHz. The demonstrated active filter occupies a small chip area of 0.47 mm x 0.33 mm excluding I/O pads and has 24 dB noise figure. Thus, an active filter with a preceding two-stage common-source LNA for suppression of noise of the active filter is also demonstrated and the resulting LNA + active filter has 6 dB noise figure. The power consumption of the active filter core and the LNA core is 9 mW and 7.2 mW, respectively.
2.4/5.7 GHz dual-band high linearity gilbert upconverter utilizing bias-offset TCA and LC current combiner
(2007-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
電信工程研究所
;
Institute of Communications Engineering
A 2.4/5.7 GHz dual-band Gilbert upconversion mixer is demonstrated using 0.35 mu m SiGe BiCMOS technology. A bias-offset cross-coupled transconductance amplifier (TCA) is employed in the intermediate frequency port for the linearity improvement. The dual-band LC current combiner and the output shunt-shunt feedback buffer amplifier are in the radio frequency (RF) port. The mechanisms of the high linearity upconverter and, the design flow of the dual-band LC current combiner are established in this letter. The dual-band upconverter has conversion gain of 1.5/-0.2 dB, OP1dB of -10.5/-9 dBm, and OIP3 of 12/13 dBm for IF=100 MHz, RF= 2.4/5.7 GHz, respectively.
2.4/5.7-GHz Dual-Band Dual-Conversion Architecture With Correlated LO Signal Generators
(2009)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Wu, Tzung-Han
;
Huang, Guo-Wei
A 2.4/5.7-GHz dual-band dual-conversion downconverter is demonstrated using 0.35-mu m SiGe hetero-junction bipolar transistor (HBT) technology. This downconverter employs a complex dual-conversion system and a complex filter to reject the first and second image signals, respectively. The LO(1) frequency is 2.5 times the LO(2) frequency and is generated by a divide-by-two divider, a frequency doubler and a single-sideband up-converter. As a result, the correlated LO signals maintain excellent image-rejection performance of the dual-conversion system while only one LO input is needed. The downconverter achieves a 40/39-dB image-rejection ratio of the first image and a 44/46-dB image-rejection ratio of the second image for 2.4/5.7-GHz modes, respectively.
30-GHz mHEMT Divide-by-Three Injection-Locked Frequency Divider With Marchand Balun
(2015)
Chang, Wei-Ling
;
Meng, Chinchun
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Tsung, Kuan-Chang
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
In this paper, the first fully integrated 0.15-mu m InAlAs/InGaAs metamorphic high electron mobility transistor (mHEMT) divide-by-three injection locked frequency divider (ILFD) with Marchand balun is demonstrated. The mHEMT technology has 110-GHz cutoff frequency and high tranconductance. Moreover, the Marchand Balun on the semi-insulating GaAs substrate has a low-loss property to provide broadband and balanced differential signals at millimeter wave frequencies. The divide-by-three ILFD performs the locking range from 28.8 GHz to 31.6 GHz under the supply voltage of 6 V and the core current consumption is 17.8 mA.
4-GHz inter-stage-matched SiGe HBT LNA with gain enhancement and no noise figure degradation
(2007-02-01)
Meng, Chinchun
;
Jhong, Jhin-Ci
;
電信工程研究所
;
Institute of Communications Engineering
An effective way to boost power gain without noise figure degradation in a cascode low noise amplifier (LNA) is demonstrated at 4 GHz using 0.35 mu m SiGe HBT technology. This approach maintains the same current consumption because a low-pass pi-type LC matching network is inserted in the inter-stage of a conventional cascode LNA. 5 dB gain enhancement with no noise figure degradation at 4 GHz is observed in the SiGe HBT LNA with inter-stage matching.