Browsing by Author "Miao, Xiang-Shui"

Now showing 1 - 7 of 7

Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing
(2018-10-01)
Wang, Zhuo-Rui
;
Li, Yi
;
Su, Yu-Ting
;
Zhou, Ya-Xiong
;
Cheng, Long
In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 10(7) cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture.
Functionally Complete Boolean Logic in 1T1R Resistive Random Access Memory
(2017-02)
Wang, Zhuo-Rui
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Su, Yu-Ting
;
Li, Yi
;
Zhou, Ya-Xiong
;
Chu, Tian-Jian
Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic.
High-Precision Symmetric Weight Update of Memristor by Gate Voltage Ramping Method for Convolutional Neural Network Accelerator
(2020-03-01)
Chen, Jia
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Pan, Wen-Qian
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Li, Yi
;
Kuang, Rui
;
He, Yu-Hui
Memristor emerges as the key enabler for neural network accelerator. Here, we demonstrate high-precision symmetric weight update in a one transistor one resistor (1T1R) structure Ti/HfO2/TiN memristor using a gate voltage ramping method, with over 120-level states and low variation (< 4%). Incorporating all experimental non-idealities, the proposed mixed hardware-software convolutional neural network demonstrates over 92.79% online learning accuracy (against software equivalent 98.45%) for MNIST recognition task. The network also shows robustness to input image noises, array yield, and retention issues.
LiSiOX-Based Analog Memristive Synapse for Neuromorphic Computing
(2019-04-01)
Chen, Jia
;
Lin, Chih-Yang
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Li, Yi
;
Qin, Chao
;
Lu, Ke
The progress in the neuromorphic computing hinges on the development of nanoscale analog artificial synapses. Here, we report a LiSiOX (LSO)-based memristive synapse with 100-level conductance states under identical pulses, representing synaptic potentiation and depression behaviors. The superior analog behaviors originate from the dynamic evolution of an electro-thermal modulation region with the motion of lithium and oxygen ions. A three-layer perceptron was constructed in simulation with LSO synapses, and a 91.97% recognition accuracy was achieved for handwritten digits. Moreover, the influences of several critical parameters, including device variability and weight precision, on the accuracy have been investigated. This letter provides guidelines for the optimization of synaptic device in robust memristive neural network.
Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array
(2017-05-28)
Zhou, Ya-Xiong
;
Li, Yi
;
Su, Yu-Ting
;
Wang, Zhuo-Rui
;
Shih, Ling-Yi
Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO2-based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.
Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation
(2019-02-01)
Hu, Si-Yu
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Li, Yi
;
Cheng, Long
;
Wang, Zhuo-Rui
;
Chang, Ting-Chang
In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a 4 x 3 array has been designed and verified in simulation.
Reducing Forming Voltage by Applying Bipolar Incremental Step Pulse Programming in a 1T1R Structure Resistance Random Access Memory
(2018-06-01)
Zheng, Hao-Xuan
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Chang, Ting-Chang
;
Xue, Kan-Hao
;
Su, Yu-Ting
;
Wu, Cheng-Hsien
This letter introduces a method of using bipolarity bias voltages in the forming process to effectively reduce the forming voltage of a one-transistor and one-resistance random access memory device. A bipolar incremental-step-pulse programming process is applied, and a complete operation pulse for the forming process is described. This method reduces forming voltage without any cost to the device performance, and the device maintains good reliability. The likely physical mechanism of this bipolar operation is also presented based on the measured electrical characteristics.