Browsing by Author "Nam, Gi-Joon"

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DATC RDF: An Academic Flow from Logic Synthesis to Detailed Routing
(2018-01-01)
Jung, Jinwook
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Jiang, Iris Hui-Ru
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Chen, Jianli
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Lin, Shih-Ting
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Li, Yih-Lang
In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing. We further include detailed placement and detailed routing tools based on recent EDA research contests. We also demonstrate RDF in a scalable cloud infrastructure. Design methodology and cross-stage optimization research can be conducted via RDF.
DATC RDF: Robust Design Flow Database
(2017-01-01)
Jung, Jinwook
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Lee, Pei-Yu
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Wu, Yan-Shiun
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Darav, Nima Karimpour
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Jiang, Iris Hui-Ru
In this paper, we present DATC Robust Design Flow Database covering the stages from logic synthesis to physical design [1]. Based on this database, design flow and cross-stage optimization research can be conducted via various EDA tools developed from academia.
Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing
(2019-01-01)
Chang, Ya-Chu
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Lin, Tung-Wei
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Jiang, Iris Hui-Ru
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Nam, Gi-Joon
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電子工程學系及電子研究所
As the wide adoption of FinFET technology in mass production, dynamic power becomes the bottleneck to achieving low power. Therefore, clock power reduction is crucial in modern IC design. Register clustering can effectively save clock power because of significantly reducing the number of clock sinks and register pin capacitance, clock routed wirelength, and the number of clock buffers. In this paper, we propose effective mean shift to naturally form clusters according to register distribution without placement disruption. Effective mean shift fulfills the requirements to be a good register clustering algorithm because it needs no prespecified number of clusters, is insensitive to initializations, is robust to outliers, is tolerant of various register distributions, is efficient and scalable, and balances clock power reduction against timing degradation. Experimental results show that our approach outperforms state-of-the-art work on power and timing balancing, as well as efficiency and scalability.
OpenDesign Flow Database: The Infrastructure for VLSI Design and Design Automation Research
(2016)
Jung, Jinwook
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Jiang, Iris Hui-Ru
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Nam, Gi-Joon
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Kravets, Victor N.
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Behjat, Laleh
Recently, there have been a slew of design automation contests and released benchmarks. ISPD place & route contests, DAC placement contests, timing analysis contests at TAU and CAD contests at ICCAD are good examples in the past and more of new contests are planned in the upcoming conferences. These are interesting and important events that stimulate the research of the target problems and advance the cutting edge technologies. Nevertheless, most contests focus only on the point tool problems instead of addressing the design flow or co-optimization among design tools. OpenDesign Flow Database platform is developed to direct attentions to the overall design flow from logic synthesis to physical design optimization [1]. The goals are to provide an academic reference design flow based on past CAD contest results, the database for design benchmarks and point tool libraries, and standard design input/output formats to build a customized design flow by composing point tool libraries.
OWARU: Free Space-Aware Timing-Driven Incremental Placement
(2016)
Jung, Jinwook
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Nam, Gi-Joon
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Reddy, Lakshmi
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Jiang, Iris Hui-Ru
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Shin, Youngsoo
This paper proposes a powerful new technique called "OWARU"(1) that re-places and re-sizes multiple gates simultaneously to improve the most critical paths of a design. In essence, it is an incremental timing-driven placement technique integrated with gate sizing optimization that runs in conjunction with static timing analysis to guarantee a WYSIWYG (2) property. The OWARU technique offers several key advantages over previous techniques such as geometrical path straightening via the Bezier-curve algorithm, free space awareness to guarantee a legal placement solution, and an accurate true timing mode. The Bezier-curve geometric smoothing algorithm is extended with new anchor placement techniques to further improve the path placement. Free space aware placement algorithm is further enhanced with multiple gate optimization. The preliminary results are promising. We applied the OWARU technique at the end of industrial strength physical synthesis optimization on high performance microprocessor designs. The technique was extremely effective in improving the most critical path of the tested designs. On timing critical paths that were not fully closed from the previous physical synthesis optimization, the WS (worst slack) is improved by 5.3% of the total clock period and the TNS (total negative slack) improved by 91.3% on average.
Smart Grid Load Balancing Techniques via Simultaneous Switch/Tie-line/Wire Configurations
(2014)
Jiang, Iris Hui-Ru
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Nam, Gi-Joon
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Chang, Hua-Yu
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Nassif, Sani R.
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Hayes, Jerry
Fast changing power distribution systems request a dynamic system configuration capability of reacting to volatile consumption demands in an economical way. Load balancing in power distribution systems is an essential technique for smart grid that enables reliable electricity delivery to end customers. This paper is the first work focusing on load balancing using switch reconfiguration, tie-line addition, and wire upgrade simultaneously, while existing works adopt only one of the three techniques to configure the power distribution system. We observe that the new load balancing problem induces a new challenge, dynamic topology rotation, which cannot be handled by existing solutions. To overcome this challenge, we first consider bidirectional power flows and formulate the load balancing problem as a mixed-integer quadratically constrained quadratic program (MIQCQP). To reduce the computational complexity, it is further transformed into a mixed-integer linear program (MILP) without loss of optimality. Experimental results show that, on real power distribution networks, our approach produces optimal solutions that arc unlikely to be found in ad-hoc heuristics methods.