Browsing by Author "Ng, Chee-Kit"

Now showing 1 - 3 of 3

A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems
(2018-01-01)
Ng, Chee-Kit
;
Lin, Yu-Chun
;
Liu, Wei-Chang
;
Wu, Chin-Feng
;
Lou, Shyh-Lye
A 40Gb/s all-digital adaptive noise-suppression feed-forward filter/equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) systems is presented. Batch mode coefficients update (BMCU) unit together with coefficients-Iookahead scheme are proposed to achieve high parallelism architecture for ADFE. With these schemes, new extended incremental coefficients-Iookahead filter architecture is proposed to provide high throughput rate and to reduce hardware complexity of parallel ADFE. Besides, feed-forward noise-suppression architecture is proposed for AFFE to provide better signal-to-noise ratio (SNR). The equalizer operates at 1 GHz system clock with 40 parallelisms is implemented in 40nm CMOS technology with a core area 0.23mm(2). The measurement results verify the equalizer performance and the maximum throughput of 40Gb/s is achieved under 0.9V supply with 4.35pJ/bit energy efficiency.
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems
(2019-01-01)
Ng, Chee-Kit
;
Lin, Yu-Chun
;
Jou, Shyh-Tye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 50Gbls all-digital adaptive noise-suppression (NS) feed-forward equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) serial link systems with SNR based power management scheme is presented. Based on a parallel extended incremental coefficients-lookahead scheme (EICL), we propose a reconfigurable Dual Data paths Self-Lookahead Filter (DD-SLF) for ADFE. SNR-power management skill is adopted to adaptively adjust the hardware configuration in different channel environment and SNR to achieve optimum energy efficiency. The whole equalizer which operates at 1 GHz system clock rate with 50 parallelisms is implemented in 40nm CMOS technology with a core area 0.38mm(2). The equalizer with 50Gb/s throughput rate achieves 2.6pJ/bit energy efficiency under 0.81V supply measurement results.
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems
(2019-01-01)
Ng, Chee-Kit
;
Chiu, Kang-Lun
;
Lin, Yu-Chun
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
A 50Gb/s all-digital adaptive noise-suppression (NS) feed-forward equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) serial link systems is presented. Based on a parallel extended incremental coefficients-lookahead scheme (EICL), we propose a Dual Data-paths Self-Lookahead Filter (DD-SLF) for ADFE. DD-SLF architecture has better energy efficiency and hardware area than an original SLF architecture due to the number of delay elements in the feedback loop is reduced. Furthermore, gated clock technique with the design idea of register file architecture is used to replace the pipelined delay elements to save power. The whole equalizer which operates at 1GHz system clock rate with 50 parallelisms is implemented in 40nm CMOS technology with a 0.38mm(2) core area. The equalizer with 50Gb/s throughput rate achieves 2.6pJ/bit energy efficiency under 0.81V supply measurement results.