Browsing by Author "Nidhi, Karuna"

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A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
(2017-07-01)
Nidhi, Karuna
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Ker, Ming-Dou
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-mu m bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (V-P) and the zero-bias drain current (I-DS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of I-D-V-D and I-D-V-G.
Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process
(2019-07-01)
Nidhi, Karuna
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Ker, Ming-Dou
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Lee, Jian-Hsing
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Huang, Shao-Chang
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交大名義發表
Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (I-AV) achieved from themodified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 000 mu m.
Energy Transformation Between the Inductor and the Power Transistor for the Unclamped Inductive Switching (UIS) Test
(2020-06-01)
Nidhi, Karuna
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Lee, Jian-Hsing
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Huang, Shao-Chang
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Ker, Ming-Dou
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交大名義發表
The fundamental model of energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test is inspected. Based on the experimental results, the energy stored in the inductor at the period of the channel turn-on can be dissipated by the power transistor after the channel is turned off. In this work, a new theoretical model to well describe the electrical and thermal behaviors of the power transistor during the unclamped inductive switching (UIS) test has been identified and analyzed with the experimental silicon results under different inductor values in 0.15 mu m BCD process. The total UIS energy reduced due to series resistance of the inductor and the power transistor has been theoretically explained and well matches with the experimental measured results on silicon.
Improving Safe-Operating-Area o f a 5-V n-Channel Large Array MOSFET in a 0.15-mu m BCD Process
(2018-07-01)
Nidhi, Karuna
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Ker, Ming-Dou
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Lin, Tingyou
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Lee, Jian-Hsing
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資訊工程學系
The safe-operating-area (SOA) of large array device (LAD) is one of the most important factors affecting the device reliability. In this paper, the improvement of the electrical-SOA (E-SOA) and the thermal-SOA (T-SOA) by using an optional implantation layer for 5-V n-channel large array MOSFET has been investigated in a 0.15-mu m bipolar-CMOS-DMOS process. Experimental results showed that the secondary breakdown current (It2) is improved by 5 times, and a significant improvement is also observed in the E-SOA and the T-SOA boundary as compared to the original device. In addition, the impact of inserting additional layout pick-ups into the multiple-finger layout of large array MOSFET to the E-SOA, It2, and trigger voltage is also practically investigated in silicon for the LAD with a total width of 12000 mu m.
Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation
(2019-01-01)
Lin, Tingyou
;
Su, Chauchin
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Hung, Chung-Chih
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Nidhi, Karuna
;
Tu, Chily
This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15tm BCD process. The measured results demonstrate a 10kjtm power MOSFET has R-on increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has R-on increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.