Browsing by Author "Nishi, Yoshio"

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Contact Engineering High-Performance n-Type MoTe2 Transistors
(2019-09-01)
Mleczko, Michal J.
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Yu, Andrew C.
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Smyth, Christopher M.
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Chen, Victoria
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Shin, Yong Cheol
Semiconducting MoTe2 is one of the few two-dimensional (2D) materials with a moderate band gap, similar to silicon. However, this material remains underexplored for 2D electronics due to ambient instability and predominantly p-type Fermi level pinning at contacts. Here, we demonstrate unipolar n-type MoTe2 transistors with the highest performance to date, including high saturation current (>400 mu A/mu m at 80 K and >200 mu A/mu m at 300 K) and relatively low contact resistance (1.2 to 2 k Omega.mu m from 80 to 300 K), achieved with Ag contacts and AlOx encapsulation. We also investigate other contact metals (Sc, Ti, Cr, Au, Ni, Pt), extracting their Schottky barrier heights using an analytic subthreshold model. High-resolution X-ray photoelectron spectroscopy reveals that interfacial metal-Te compounds dominate the contact resistance. Among the metals studied, Sc has the lowest work function but is the most reactive, which we counter by inserting monolayer hexagonal boron nitride between MoTe2 and Sc. These metal-insulator-semiconductor (MIS) contacts partly depin the metal Fermi level and lead to the smallest Schottky barrier for electron injection. Overall, this work improves our understanding of n-type contacts to 2D materials, an important advance for low-power electronics.
Contact Engineering of Trilayer Black Phosphorus With Scandium and Gold
(2019-01-01)
Tsai, Yi-Chia
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Magyari-Kope, Blanka
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Li, Yiming
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Samukawa, Seiji
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Nishi, Yoshio
High contact resistance keeps black phosphorus (BP) from fully wielding its excellent material property. Using first-principles calculations, we analyze the interfacial binding behavior and the impact of binding on the other layers of a trilayer BP. We found that the interfacial charge density and charge transfer of Scandium (Sc)-contacted trilayer BP are 2.67 and 3.29 times greater than Au-contacted trilayer BP, respectively. Moreover, the interfacial tunneling barrier height and width of Sc-contacted trilayer BP are 0 eV and 1.851 angstrom, which are significantly smaller than that of 5.1 eV and 2.447 angstrom observed in Au-contacted trilayer BP. All these facts suggest a strong bonding and efficient carrier transmission between Sc contact and trilayer BP substrate. Therefore, we conclude that the Sc electrode can lead to a superior performance that is consistent with the experiment.
Design and Optimization Methodology for 3D RRAM Arrays
(2013)
Deng, Yexin
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Chen, Hong-Yu
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Gao, Bin
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Yu, Shimeng
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Wu, Shih-Chieh
3D RRAM arrays are studied at the device-and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.
Effects of postgate dielectric treatment on germanium-based metal-oxide-semiconductor device by supercritical fluid technology
(2010-03-15)
Liu, Po-Tsun
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Huang, Chen-Shuo
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Huang, Yi-Ling
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Lin, Jing-Ru
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Cheng, Szu-Lin
Supercritical fluid (SCF) technology is employed at low temperature as a postgate dielectric treatment to improve gate SiO(2)/germanium (Ge) interface in a Ge-based metal-oxide-semiconductor (Ge-MOS) device. The SCF can transport the oxidant and penetrate the gate oxide layer for the oxidation of SiO(2)/Ge interface at 150 degrees C. A smooth interfacial GeO(2) layer between gate SiO(2) and Ge is thereby formed after SCF treatment, and the frequency dispersion of capacitance-voltage characteristics is also effectively alleviated. Furthermore, the electrical degradation of Ge-MOS after a postgate dielectric annealing at 450 degrees C can be restored to a extent similar to the initial state.
Improved Multi-level Control of RRAM Using Pulse-Train Programming
(2014-01-01)
Zhao, Liang
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Chen, Hong-Yu
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Wu, Shih-Chieh
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Jiang, Zizhen
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Yu, Shimeng
Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.