Browsing by Author "Niu, Dow-Chi"

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A DC-20GHz CMOS Active Power Divider Design
(2010-01-01)
Huang, Jing-Ying
;
Wu, Hui-I
;
Hu, Robert
;
Jou, Christina F.
;
Niu, Dow-Chi
We report the design of a wideband active power divider using commercial CMOS process. This circuit is made of two distributed amplifiers sharing a common input artificial transmission line while two distinct transmission lines are employed for the output ports. Since the input transmission line tends to be overly capacitive now when compared with the conventional distributed amplifier, the constituting gain cells need to be revised so as to retain the intended 20GHz bandwidth. Small input and output reflection coefficients have been observed, and the measured output port isolation is below -30dB across the whole bandwidth, which is beyond the reach of passive power dividers. Magnitude and phase imbalances of the two output ports are 0.2dB and 0.4 degrees at 15GHz and 0.9dB and 0.6 degrees at 20GHz. The noise figure is 6.9dB at 15GHz and 9.4dB at 20GHz. The input-referred 1dB compression point is -9.5dBm at 15GHz and -10.5dBm at 20GHz. With the bias of 2.5Volt and 64Amp, the total power dissipation is 160mWatt.
Analysis and design of wideband active power splitter with interleaf transmission line topology
(2019-11-01)
Huang, Ching-Ying
;
Hu, Robert
;
Niu, Dow-Chi
;
Chang, Chi-Yang
;
電機學院
This article proposes a new wideband active power splitter design where the gain cells along the input transmission line are arranged in interleaf rather than the conventional parallel style, thus the circuit's high-frequency performance can be greatly improved. Both theoretical analysis and circuit simulation have been carried out; as a demonstration, parallel and interleaf active power splitters are designed using 0.1 mu m GaAs pseudo-morphic heterostructure field effect transistors (GaAs pHEMT) process and measured on-wafer. The results clearly indicate the superiority of the interleaf topology. A 40 GHz interleaf active power splitter in 90 nm complementary metal-oxide-semiconductor (CMOS) is then presented where the magnitude and phase imbalance between the two output ports are 0.15 dB and 2.6 degrees at 20 GHz, and 0.16 dB and 14 degrees at 40 GHz. The output-port isolation is better than 30 dB across the whole frequency range.