Browsing by Author "Ong, KK"

Now showing 1 - 4 of 4

A high throughput context-based adaptive arithmetic codec for JPEG2000
(2002)
Ong, KK
;
Chang, WH
;
Tseng, YC
;
Lee, YS
;
Lee, CY
In JPEG2000 image compression standard, context-based arithmetic coding is adopted for improving compression rate. Efficient and high throughput codec: design is strongly required for handling high-resolution images. We propose an efficient architecture for context-based adaptive arithmetic coding, which can achieve high throughput performance. Based on parallel leading zeros detection and bit-stuffing handling, symbol can be encoded and decoded within one cycle. Therefore, throughput rate can be increased as high as codec operating frequency. The modified encoding and decoding flows are compatible with JPEG2000 standard. For 0.35u 1P4M CMOS technology, encoding and decoding rate can run up to 200Msymbol/sec and 175Msymbol/sec respectively. They are only cost 6.8K and 9.8K gate count. These high throughput performances can meet high-resolution real time application requirement.
A high throughput low cost context-based adaptive arithmetic codec for multiple standards
(2002)
Ong, KK
;
Chang, WH
;
Tseng, YC
;
Lee, YS
;
Lee, CY
For next generation image compression standard, context-based arithmetic coding is adopted for improving compression rate. Efficient and high throughput codec design is strongly required for handling high-resolution images. We propose an efficient codec architecture for context-based adaptive arithmetic coding, which exhibits low cost, low latency, and high throughput rate. In addition, it can be programmed for supporting multiple standards such as JPEG, JPEG2000, JBIG, and JBIG2 standards. It is exploiting three-pipeline stages architecture. Based on parallel leading zeros detection and bit-stuffing handling, symbol can be encoded and decoded within one cycle. Therefore, throughput rate can be increased as high as codec operating clock rate. For 0.35u 1P4M CMOS technology, both encoding and decoding rate can run up to 185Msymbol/sec. The AC codec only costs 12K gate count and 860um x 860um layout area. These performances can meet high-resolution real time application requirement.
Error resilient image coding and smart post-processing error concealment for wireless image transmission
(2002)
Ong, KK
;
Lee, YS
;
Lee, CY
;
交大名義發表
;
National Chiao Tung University
Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission
(2003-02-01)
Lee, YS
;
Ong, KK
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The fields of multimedia and wireless communications have grown rapidly in recent years, leading to a great demand for an image-coding scheme that has both compression and error-resilient capabilities. Because bandwidth is a valuable and limited resource, the compression technique is applied to wireless multimedia communication. However, strong data dependency will be created while the bit-rate reduction is achieved. Transmission errors always results in significant quality degradation. In this paper, an error-resilient image coding for discrete-cosine-transform-based image compression is proposed. It can successfully prevent errors from propagating across image block boundaries with little overhead. Additionally, a. novel Post-processing error concealment. scheme is presented to retain low-frequency information and discard suspicious high-frequency information. Low-resolution information, rather than total corruption, can be obtained during the image-decoding process. Because of low complexity and latency properties, it is very suitable for wireless mobile applications. Simulation results show that good image quality (PSNR = 31.78dB) and a low fraction of corruptive blocks (less than 5%) can be achieved even when the bit error rate is 0.1%.