Browsing by Author "Ou, Shih-Hao"

Now showing 1 - 7 of 7

A 52mW 1200MIPS compact DSP for multi-core media SoC
(2006)
Ou, Shih-Hao
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Lin, Tay-Jyi
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Huang, Chao-Wei
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Kuo, Yu-Ting
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Chao, Chie-Min
This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.
A controllable low-power dual-port embedded SRAM for DSP processor
(2008)
Yang, Hao-I
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Chang, Ming-Hung
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Lin, Tay-Jyi
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Ou, Shih-Hao
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Deng, Siang-Sen
In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A codesign of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable precharged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.
A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor
(2016-04)
Liu, Chih-Wei
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Ou, Shih-Hao
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Chang, Kuo-Chiang
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Lin, Tzung-Ching
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Chen, Shin-Kai
Based on an error-flattened, non-uniform-region linear-approximation algorithm, this brief proposes a low-error and a cost-efficient design procedure for realizing an optimized shift-and-add Logarithmic Unit (LU), which uses minimum hardware to meet the desired error constraint for embedded graphics systems. Mathematically, this brief first derives two solutions of the error-flattened algorithm. Subsequently, for an error constraint, the minimum number of approximation regions, n, the corresponding i th interpolation coefficients (a(i), b(i)), and the regional endpoints (x(i-1), x(i)), 1 <= i <= n, are obtained accordingly. Using the unique properties of the logarithmic function, spacing of x(i) is non-uniform to make errors in each region consistent. Carefully examining the cost of the applied add/sub network, a low-cost candidate for a shift-and-add LU is determined. Next, a cost exploration process, which gradually increases n, is performed. A large number of regions results in a more accurate conversion algorithm that might tolerate more implementation errors by using simple hardware whose cost is lower than that of the inferior candidate. After exploring the cost based on error tolerance, the proposed design procedure finally generates a hardware to meet the desired error constraint. Slightly modifying the regional endpoint x(i) increases hardware efficiency at the cost of increased error. Proposed circuits were synthesized in UMC 65RVT CMOS technology. Compared to state-of-the-art shift-and-add logarithmic converters, simulation results reveal that the proposed design saves approximately 12.7-51.1 percent area of polynomial approximation and improves approximately 1-14-dB SNR gain while achieving a tighter error constraint.
A Smart Stream Controller for Efficient Implementation of Streaming Applications on the Heterogeneous Multicore Processor
(2012)
Ou, Shih-Hao
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Yeh, Che-Wei
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Lin, Tai-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
Recently, many embedded systems adopt the heterogeneous multi-core processors, such as the TI OMAP and the IBM Cell BE, to allow offloading computation-intensive tasks from the MPU to the DSP for satisfying the increasing complexity of the emerging DSP streaming applications, such as the audio/video coding. By conventional parallel programming, task management is handled by the MPU with the OS or runtime assist. However, the thick OS stack or the laborious task management will significantly degrade the performance. This paper proposed a dedicated programmable smart stream controller, conforming to the streaming computation, to offload the task management from the MPU to greatly reduce runtime overhead. The smart stream controller provides a set of simple and high-level APIs to facilitate parallel programming on the heterogeneous multi-core processors. In our 512x512 JPEG encoding simulations, the proposed dedicated smart stream controller achieves up to 80% performance improvement compared to its software counterpart, i.e. implementing a runtime on MPU. Additionally, the performance scalability and capability of the smart stream controller to take advantage of architectural parallelism, adapting to varying number of DSP cores, are also presented.
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids
(2015-01-01)
Ou, Shih-Hao
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Chang, Kuo-Chiang
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital hearing aids. In the proposed SFP LPFIR (linear-phase finite impulse response) filter engine, lower silicon area and lesser power consumption facilitate better SNR performance than that achieved with the conventional post-truncation (PT) datapath with integer arithmetic. Moreover, in the proposed LPFIR filter engine, a cascaded 16-bit SFP A-M-S-Acc datapath is used that consists of two embedded 1-bit shifters to improve hardware usage and parallelism, one 16-bit DT adder (A), one 16-bit DT multiplier (M), one 16-bit barrel shifter (S), and one 16-bit DT accumulator (Acc). The operations per cycle (OPC) of the proposed SFP LPFIR filter engine reaches 6, which enables efficient fabrication of the low-latency AFB for hearing aids. To verify the effectiveness of the proposed 16-bit SFP LPFIR filter engine, a 10-ms 18-band quasi-ANSI S1.11 1/3-octave AFB for digital hearing aids was implemented using UMC 90-nm CMOS technology. The AFB was operated at 792 kHz to process, in real-time, 24 kHz audio, with the power consumption being approximately 80.6 mu W (at 1 V). Compared to the previous design in which the conventional PT datapath with integer arithmetic was used, approximately 9.6% of total power and 83% of silicon area were saved and almost the same SNR (signal-to-noise ratio) performance was achieved with the new system, when evaluated by a 3.96-s sequence of Mandarin speech. (C) 2014 Elsevier B.V. All rights reserved.
Improving datapath utilization of programmable DSP with composite functional units
(2008)
Ou, Shih-Hao
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Cho, Yi
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Lin, Tay-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
A scalar (single-issue) processor executes one instruction at a time and its functional units (ALU, multiplier, and shifter, etc) are never concurrently exercised. Modem processors issue multiple instructions simultaneously (i.e. superscalar or VLIW) to improve their functional unit utilization but the cost is considerably high. In this paper, an alternative is described to activate multiple functional units concurrently by issuing a composite instruction on cascaded functional units. Besides, an automatic generator for application-specific composite functional units is presented. In our simulation with popular DSP applications, 35% increase on the operations per cycle ran be simply obtained with identical functional units. Moreover, our proposed approach saves up to 16.5% and 31.6% power on scalar and VLIW respectively for comparable performance.
Multithreaded coprocessor interface for multi-core multimedia SoC
(2008)
Ou, Shih-Hao
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Lin, Tay-Jyi
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Deng, Xiang Sheng
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Zhuo, Zhi Hong
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Liu, Chih Wei
Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management Is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.