Browsing by Author "Pan, David Z."

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A High-Performance Triple Patterning Layout Decomposer with Balanced Density
(2013)
Yu, Bei
;
Lin, Yen-Hung
;
Luk-Pat, Gerard
;
Ding, Duo
;
Lucas, Kevin
Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e. g., by Yu et al. (ICCAD\'11), Fang et al. (DAC\'12), and Kuang et al. (DAC\'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline.
DOPPLER: DPL-aware and OPC-friendly Gridless Detailed Routing with Mask Density Balancing
(2011)
Lin, Yen-Hung
;
Ban, Yong-Chan
;
Pan, David Z.
;
Li, Yih-Lang
;
資訊工程學系
The printed image of a layout that satisfies the double patterning lithograph (DPL) constraints may not have good fidelity if the layout neglects optical proximity correction (OPC). Simultaneously considering DPL and OPC becomes necessary when generating layouts, especially in routing stage. Moreover, one decomposed design with balanced mask density has a lower edge placement error (EPE) than an unbalanced one [6]. This work proposes a comprehensive conflict graph (CCG) to enable detailed routers to simultaneously consider DPL, OPC, and mask density to generate litho-friendly layouts. This work then develops an DPL-aware and OPC-friendly gridless detailed routing (DOPPLER) by applying CCG in a gridless routing model. A density variation threshold annealing-based routing flow is also proposed to prevent DOPPLER from falling into a sub-optimal mask density balance. Compared with existing DPL-aware detailed routing works, DOPPLER demonstrates an average 73.84% of EPE hotspot reduction with a satisfactory mask density at the cost of an average increase of 0.08% wire-length, 15.14% number of stitches, and 77.28% runtime.
TRIAD: A Triple Patterning Lithography Aware Detailed Router
(2012)
Lin, Yen-Hung
;
Yu, Bei
;
Pan, David Z.
;
Li, Yih-Lang
;
資訊工程學系
TPL-friendly detailed routers require a systematic approach to detect TPL conflicts. However, the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG. This work proposes a token graph-embedded conflict graph (TECG) to facilitate the TPL conflict detection while maintaining high coloring-flexibility. We then develop a TPL aware detailed router (TRIAD) by applying TECG to a gridless router with the TPL stitch generation. Compared to a greedy coloring approach, experimental results indicate that TRIAD generates no conflicts and few stitches with shorter wirelength at the cost of 2.41 x of runtime.