Browsing by Author "Pan, Po-Cheng"

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A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation
(2015-09-01)
Pan, Po-Cheng
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Chin, Ching-Yu
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Chen, Hung-Ming
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Chen, Tung-Chieh
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Lee, Chin-Chieh
Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper first introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation. And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variable-gain amplifier, a folded-cascode operational amplifier, and a low dropout regulator. The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.
A Stochastic-Based Efficient Critical Area Extractor on Open Access Platform
(2009-01-01)
Chen, Bo-Zhou
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Chen, Hung-Ming
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Huang, Li-Da
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Pan, Po-Cheng
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電子工程學系及電子研究所
Due to inefficient calculation in current critical area analyzer, in this work we present a method of extracting critical area for short faults from the mask layout of an integrated circuit. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more efficient, thus more suitable for the larger layout. The algorithm has been implemented on OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost, and can still maintain the accuracy at the same time.
A Stochastic-Based Efficient Critical Area Extractor on Open Access Platform
(2009-01-01)
Chen, Bo-Zhou
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Chen, Hung-Ming
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Huang, Li-Da
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Pan, Po-Cheng
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電子工程學系及電子研究所
Due to inefficient calculation in current critical area analyzer, in this work we present a method of extracting critical area for short faults from the mask layout of an integrated circuit. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more efficient, thus more suitable for the larger layout. The algorithm has been implemented on OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost, and can still maintain the accuracy at the same time.
An Automatic Synthesis Tool for Nanometer Low Dropout Regulator Using Simulation Based Model and Geometric Programming
(2014-01-01)
Hsu, Shih-Hsin
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Chen, Wei-Zen
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Zheng, Jui-Pin
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Liu, Sean S. -Y.
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Pan, Po-Cheng
This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the "SPICE accuracy" device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.
Analog Placement with Current Flow and Symmetry Constraints using PCP-SP
(2018-01-01)
Patyal, Abhishek
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Pan, Po-Cheng
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Asha, K. A.
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Chen, Hung-Ming
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Chi, Hao-Yu
Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This paper proposes the first work that reformulates this problem considering all of them together in the form of Parallel Current Path (PCP) constraints. Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. Experimental results show that this formulation and algorithm can satisfy all the constraints in a more tightly packed configuration, resulting in lesser routing length, reduced parasitics and thus better post-layout performance.
Configurable Analog Routing Methodology via Technology and Design Constraint Unification
(2012)
Pan, Po-Cheng
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Chen, Hung-Ming
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Cheng, Yi-Kan
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Liu, Jill
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Hu, Wei-Yi
In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are unified through schematic level to layout level. In contrast to self-defined constraint format in prior arts, proposed approach manipulates the analog routing characteristic based on the unified constraints. In different circuit hierarchies defined by circuit designers or extracted by existing placement, the hierarchical structure is formed as specific analog layout constraint groups. This work efficiently facilitates analog routing strategy which honors the specific analog constraints. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact.
Efficient Analog Layout Prototyping by Layout Reuse with Routing Preservation
(2013)
Chin, Ching-Yu
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Pan, Po-Cheng
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Chen, Hung-Ming
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Chen, Tung-Chieh
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Lin, Jou-Chun
To strive for better circuit performance on analog design, layout generation heavily relies on experienced analog designers' effort. Other than general analog constraints such as symmetry and wire-matching are commonly embraced in many proposed works, analog circuit performance is also sensitive to routing behavior. This paper presents a CDT-based layout extraction to preserve routing behavior of the reference layout. Furthermore, a generalized layout prototyping methodology is proposed based on the layout extraction to achieve routing reuse. The proposed layout prototyping is applied to a variable-gain amplifier and a folded-cascode operational amplifier for both migration and prototypes generation. Experimental results show that our approach effectively reduces design cycle time and simultaneously produces reasonable performance.
Fast Analog Layout Prototyping for Nanometer Design Migration
(2011)
Weng, Yi-Peng
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Chen, Hung-Ming
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Chen, Tung-Chieh
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Pan, Po-Cheng
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Chen, Chien-Hung
This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.
Late Breaking Results: An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis
(2019-01-01)
Pan, Po-Cheng
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Huang, Chien-Chia
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An efficient synthesis technique for modern analog circuits is important yet challenging due to the repeatedly re-synthesis process. To precisely explore the analog circuit performance limitation on the required technology is time-consuming. This work presents a learning-based framework for searching the limitation of analog circuits. With hierarchical architecture, the dimension of solution space can be reduced. Bayesian linear regression and support vector machine model are selected to speed up the algorithm and better performance quality can be retrieved. Experimental results show that our approach on two analog circuits can achieve up to 9x runtime speed-up without surrendering performance qualities.
On Closing the Gap Between Pre-simulation and Post-simulation Results in Nanometer Analog Layouts
(2018-01-01)
Pan, Po-Cheng
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Huang, Hung-Wen
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Huang, Chien-Chia
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Patyal, Abhishek
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Chen, Hung-Ming
In order to generate analog layout in advanced technology, it still remains lots of challenges due to the imprecise estimation of critical performance parameters. We propose an upgraded decision making framework, PEDefer, to decompose existing layout into decisive components for performance estimation. In this work, the objective is to synthesize layout solutions based on the performance estimation of user-defined constraints and existing templates. The constraints of the circuit are priorly tackled in the partition and layout enumeration stage. In addition, we attempt to have partial layout pieces as exchangeable blocks to perform pseudo-post-simulation, thus to put simulation factors in the evaluation during layout enumeration strategy. The experiments show that this flow guarantees valid analog layout results whose performances are closer to netlist-level simulation than manual designed or migrated layouts with minimal overhead.
PAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Design
(2013-01-01)
Pan, Po-Cheng
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Chen, Hung-Ming
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Lin, Chien-Chih
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an agile hierarchical synthesis framework for analog circuit. To acknowledge the limitation for a given topology analog circuit, this hierarchical synthesis work proposes a performance exploration technique and a non-uniform-step simulation process. Apart from spec targeted designs, this proposed approach can help to search the solutions better than designers' expectation. A parallel genetic algorithm (PAGE) method is employed for performance exploration. Unlike other evolution-based topology explorations, this is the first method that regards performance constraints as input genome for evolution and resolves the multiple-objective problem with the multiple-population feature. Populations of selected performance are transfered to device variables by re-targeting technique. Based on a normalization of device variable distribution, a probabilistic stochastic simulation significantly reduces the convergence time to find the global optima of circuit performance. Experimental results show that our approach on radio-frequency distributed amplifier (RFDA) and folded cascode operational amplifier (Op-Amp) in different technologies can obtain better runtime and higher quality in analog synthesis.