Browsing by Author "Pan, SR"

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Crosstalk-constrained performance optimization by using wire sizing and perturbation
(2000)
Pan, SR
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Chang, YW
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資訊工程學系
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Department of Computer Science
In this paper, we propose a unified wire sizing and perturbation algo rithm for crosstalk-constrained performance optimization that is applicable to general routing structures. Our algorithm is based on a two-stage iterative technique: we first perturb all wires to the positions with the minimum delay, then we adjust the wire sizes to further optimize delay under crosstalk constraints. The unified wire sizing and perturbation technique has the property of unimodality, implying that there is a unique position resulting in the optimal delay and crosstalk. Applying these properties can dramatically reduce the search space and thus lead to a very efficient method to determine the best wire position and the optimal wire size. Experimental results show that our algorithm can achieve average improvements of 44.5% and 40.2% in delay without sacrificing area and crosstalk for the 0.18 mum and 0.25 mum process technologies, respectively. Further, we develop an effective incremental update technique that can substantially speed up the runtime. Empirically, this technique can reduce runtime by 10 times.
Reliable crosstalk-driven interconnect optimization
(2006-01-01)
Jiang, IHR
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Pan, SR
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Chang, YW
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Jou, JY
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電子工程學系及電子研究所
As technology advances apace, crosstalk becomes a design metric of comparable importance to area and delay. This article focuses mainly on the crosstalk issue, specifically on the impacts of physical design and process variation on crosstalk. While the feature size shrinks below 0.25 mu m, the impact of process variation on crosstalk increases rapidly. Hence, a crosstalk insensitive design is desirable in the deep submicron regime. In this article, crosstalk sensitivity is referred to as the influence of process variation on crosstalk in a circuit. We show that the lower bound of crosstalk sensitivity grows quadratically, while that of crosstalk increases linearly. Therefore, designers should also consider crosstalk sensitivity, when optimizing other design objectives such as crosstalk, area, and delay. According to our modeling, these objectives are all in posynomial forms, and thus the multiobjective optimization problem can optimally be solved by Lagrangian relaxation. Experimental results show that our method is effective and efficient. For instance, a circuit of 2856 gates and 5272 wires is optimized using 13-minute runtime and 2.8-MB memory on a Pentium III 1.0 GHz PC with 256-MB memory. In particular, by relaxing Lagrange multipliers to the critical paths, it takes only two iterations for all solutions to converge to the global optimal, which is much more efficient than related previous work. This relaxation scheme provides a key insight into the rapid convergence in Lagrangian relaxation.