Browsing by Author "Pan, Samuel C."
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Item type:Item, A novel array-based test methodology for local process variation monitoring(2009) ;Luo, Tseng-Chin ;Chao, Mango C. -T. ;Wu, Michael S. -Y. ;Li, Kuo-TsaiHsia, Chin C.As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for IC manufacturing. To monitor local process variation, a large number of DUTs (device-under-test) in close proximity must be measured. In this paper, we presents a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by utilizing the proposed hardware IR compensation and voltage bias elevation. Furthermore, the DUT layout need not be modified for the proposed test structure so that the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.Item type:Item, A Novel Array-Based Test Methodology for Local Process Variation Monitoring(2011-05-01) ;Luo, Tseng-Chin ;Chao, Mango C. -T. ;Wu, Michael Shien-Yang ;Li, Kuo-TsaiHsia, Chin C.As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for integrated circuit manufacturing. To monitor local process variation, a large number of devices-under-test (DUTs) in close proximity must be measured. In this paper, we present a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by application of the test techniques proposed in this paper: hardware IR compensation, voltage bias elevation, and leakage-current cancelation. Furthermore, the DUT layout need not be modified for the proposed test structure. Thus, the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.Item type:Item, Impact of self-heating effect on hot carrier degradation in high-voltage LDMOS(2007) ;Cheng, Chih-Chang ;Lin, J. F. ;Wang, Tahui ;Hsieh, T. H.Tzeng, J. T.Self-heating induced transient hot carrier effects in high-voltage n-LDMOS are investigated. A novel LDMOS structure incorporating a metal contact in the bird's beak region is fabricated, which allows us to probe an internal voltage transient in hot carrier stress. The AC stress-frequency dependence of device degradation is characterized and evaluated by a two-dimensional numerical simulation. Our result shows that drain current degradation in AC stress is more serious than in DC stress because of the reduction. of self-heating effect.Item type:Item, Physics and characterization of various hot-carrier degradation modes in LDMOS by using a three-region charge-pumping technique(2006-09-01) ;Cheng, Chih-Chang ;Lin, J. F. ;Wang, Tahui ;Hsieh, T. H.Tzeng, J. T.Degradation of lateral diffused MOS transistors in various hot-carrier stress modes is investigated. A novel three-region charge-pumping technique is proposed to characterize interface trap (Nit) and bulk oxide charge Q(ox) creation in the channel and in the drift regions separately. The growth rates of N-it and Q(ox) are extracted from the proposed method. A two-dimensional numerical device simulation is performed to gain insight into device degradation characteristics in different stress conditions. This paper shows that a maximum I-g stress causes the largest drain current and subthreshold slope degradation because of both N-it generation in the channel and Q(ox) creation in the bird's beak region. The impact of oxide trap property and location on device electrical characteristics is analyzed from measurement and simulation.