Browsing by Author "Pao, Chia-Hao"

Now showing 1 - 2 of 2

A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
(2012)
Pao, Chia-Hao
;
Fan, Ming-Long
;
Tsai, Ming-Fu
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S. S.), V-T, 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN Delta I-D/I-D amplitude and larger Delta V-T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.
Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
(2013)
Tsai, Ming-Fu
;
Fan, Ming-Long
;
Pao, Chia-Hao
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
This paper discusses the design and optimization of 6T SRAM cell using multiple stacked NanoWire (NW) MOSFETs. The results suggest that RSNM reaches the maximum when Pull-Up (PU) and Pull-Down (PD) transistors are stacked in equivalent number. Up to 40% and 91% improvement in RSNM are achieved at the cost of 7.5% and 5.9% degradation in WSNM using Floating-Power Write-assist compared with the case without stacking at V-DD = 0.3V and 1V, respectively. For robust design in subthreshold SRAM, raising V-trip by stacking PU transistors is more efficient than reducing Read disturb by stacking PD transistors under the premise of using quantized number of stacked NW. Moreover, we show that the stacked NW MOSFETs suppress the impact of Line-Edge Roughness (LER) variation and mitigate the variability in SRAM.