Browsing by Author "Patyal, Abhishek"

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Analog Placement with Current Flow and Symmetry Constraints using PCP-SP
(2018-01-01)
Patyal, Abhishek
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Pan, Po-Cheng
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Asha, K. A.
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Chen, Hung-Ming
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Chi, Hao-Yu
Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This paper proposes the first work that reformulates this problem considering all of them together in the form of Parallel Current Path (PCP) constraints. Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. Experimental results show that this formulation and algorithm can satisfy all the constraints in a more tightly packed configuration, resulting in lesser routing length, reduced parasitics and thus better post-layout performance.
Generation of PUP-Keys on FPGAs by K-means Frequency Clustering
(2018-01-01)
Asha, K. A.
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Patyal, Abhishek
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Chen, Hung-Ming
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交大名義發表
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電子工程學系及電子研究所
Physical Undonable functions (PUFs) generate secret keys that are unique and derived from the manufacturing process variations of the device. For high-security applications, generating the keys on the device is more secure than storing it on the device due to its resistance to attacks like tampering, probing and side-channel attacks. Also, the PUF-key generated should be very unique and reliable. In this paper, we are proposing a novel technique of generating a Ring Oscillator (RO) based PUF-keys on FPGAs by K-means clustering of RO frequencies. The placement of ROs on the FPGA fabric will have an impact on the variation of their oscillating frequencies. Based on the similarities in their frequency variations, the RO frequencies are grouped into k-clusters by K-means clustering and, the comparison of within-cluster RO frequencies will generate the PUF-keys. Our proposed method is evaluated on a large population of 193 Xilinx Spartan FPGAs. With the proposed method, the average inter die Ramming Weight of the PUF responses is 48.92% which is close to the ideal value of 50%, the average Ramming Weight of the n-bit PUF response is 49.90% and the average error rate due to changes in temperature and voltage is 3.43%.
On Closing the Gap Between Pre-simulation and Post-simulation Results in Nanometer Analog Layouts
(2018-01-01)
Pan, Po-Cheng
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Huang, Hung-Wen
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Huang, Chien-Chia
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Patyal, Abhishek
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Chen, Hung-Ming
In order to generate analog layout in advanced technology, it still remains lots of challenges due to the imprecise estimation of critical performance parameters. We propose an upgraded decision making framework, PEDefer, to decompose existing layout into decisive components for performance estimation. In this work, the objective is to synthesize layout solutions based on the performance estimation of user-defined constraints and existing templates. The constraints of the circuit are priorly tackled in the partition and layout enumeration stage. In addition, we attempt to have partial layout pieces as exchangeable blocks to perform pseudo-post-simulation, thus to put simulation factors in the evaluation during layout enumeration strategy. The experiments show that this flow guarantees valid analog layout results whose performances are closer to netlist-level simulation than manual designed or migrated layouts with minimal overhead.