Browsing by Author "Peng, An-Sam"

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An Improved EEHEMT RF Noise Model for 0.25 mu m InGaP pHEMT Transistor Using Verilog-A Language
(2017-05-01)
Peng, An-Sam
;
Wu, Lin-Kun
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, an accurate experimental noise model to improve the EEHEMT nonlinear model using the Verilog-A language in Agilent ADS is presented for the first time. The present EEHEMT model adopts channel noise to model the noise behavior of pseudomorphic high electron mobility transistor (pHEMT). To enhance the accuracy of the EEHEMT noise model, we add two extra noise sources: gate shot noise and induced gate noise current. Here we demonstrate the power spectral density of the channel noise S-id and gate noise S-ig versus gate-source voltage for 0.25 mu m pHEMT devices. Additionally, the related noise source parameters, i.e., P, R, and C are presented. Finally, we compare four noise parameters between the simulation and model, and the agreement between the measurement and simulation results shows that this proposed approach is dependable and accurate.
Miniature RF test structure for on-wafer device testing and in-line process monitoring
(2008-01-01)
Cho, Ming-Hsiang
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Lee, Ryan
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Peng, An-Sam
;
Chen, David
;
Yeh, Chune-Sin
In this brief, a miniature test structure for RF device characterization and process monitoring has been proposed. This new layout design can minimize the voltage drop across interconnects and can prevent capacitive coupling to devices. It consumes only 36% and 40% of the chip area of the conventional on-wafer and in-line test structures, respectively. The RF characteristics of the proposed test structure are shown to be in excellent agreement with those of the conventional ones.
Through-Silicon-Via Characterization and Modeling Using a Novel One-Port De-Embedding Technique
(2013-10-01)
Peng, An-Sam
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Cho, Ming-Hsiang
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Wang, Yueh-Hua
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Wang, Meng-Fang
;
Chen, David
In this paper, a novel and simple one-port de-embedding technique has been applied to through-silicon-via (TSV) characterization and modeling. This method utilized pad, via, and line structures to extract the equivalent circuit model of TSV. The main advantage of this de-embedding method is that it can reduce the chip area to fabricate test element groups (TEGs) for measurements while keeping S-parameter measurement accuracies. We also analyzed the electrical characteristics of substrate coupling and TSV equivalent impedance. Our results shows good agreements between measurement data and the equivalent circuit model up to 20 GHz.