Browsing by Author "Peng, Chi-Wei"

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A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM
(2006)
Hua, Chung-Hsien
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Peng, Chi-Wei
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel AND-type match-line scheme with XOR-based conditional keeper for ternary content-addressable memory (TCAM) are presented in this paper. The XOR-based conditional keeper is turned off at some critical moments to reduce the search time and power consumption. High fan-in AND-type match-line schemes are used to demonstrate the effectiveness of the XOR-based conditional keeper in the presence of noise sources. 37.8% search time reduction and 15.6% power saving are achieved by using the proposed TCAM architecture. Based on TSMC 0.13 mu m CMOS technology at 1.2V supply voltage, a 256 words x 128 bits ternary CAM is designed. The simulation results show that the search time of proposed TCAM architecture is 1.17ns and energy metric of proposed TCAM architecture is 0.7520/search.
Testing Methods for Quaternary Content Addressable Memory Using Charge-Sharing Sensing Scheme
(2015)
Yang, Hao-Yu
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Huang, Rei-Fu
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Su, Chin-Lung
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Lin, Kuan-Hong
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Shu, Hang-Kaung
Due to its capability of parallel search, content addressable memory (CAM) has been widely used on the applications requiring high-speed data search. In recent years, the architectures and design techniques for CAM have been consistently evolving. However, the incoming testing issues for those newly evolved CAM designs are not fully discussed. In this paper, we investigate the testing issues for a new 28nm quaternary CAM, which provides the additional fourth state compared to a conventional ternary CAM and utilizes a charge-sharing sensing scheme for reducing its search power consumption. We first identify the new fault models for this quaternary CAM that are not covered in the conventional CAM testing based on the simulation result, and derive the corresponding test algorithm for those new fault models. The effectiveness of the proposed test algorithm is then validated by the testing result of 7200 28nm sample chips covering different process corners with the help of a newly designed command-based memory BIST.
XOR-based conditional keeper and an architecture implementing its application to match lines
(2007-05-10)
Hua, Chung-Hsien
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Peng, Chi-Wei
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Hwang, Wei
The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed. Further, the XOR-based conditional keeper of the present invention can also apply to all kinds of dynamic circuits, particularly to a high fan-in circuit.