Browsing by Author "Peng, JJ"

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Active device under bond pad to save I/O layout for high-pin-count SOC
(2003-01-01)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-mum one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
(2001)
Ker, MD
;
Jiang, HC
;
Peng, JJ
;
Shieh, TL
;
電子工程學系及電子研究所
A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.
Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuits
(2003)
Ker, MD
;
Hsu, HC
;
Peng, JJ
;
電機學院
;
College of Electrical and Computer Engineering
A novel electrostatic discharge (TSD) implantation method is proposed to significantly improve machine-model (MM) ESD robustness of NMOS device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300mum/0.5 mum for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25-mum CMOS process. This ESD implantation, method with the n-type impurity is fully process-compatible to general sub-quarter-micron CMOS processes.
ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness
(2003-10-01)
Ker, MD
;
Hsu, HC
;
Peng, JJ
;
電機學院
;
College of Electrical and Computer Engineering
A new electrostatic discharge (ESD) implantation method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 mum/0.5 mum has been successfully improved from the original 450 V to become 675 V in a 0.25-mum CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 mum/0.5 mum for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation Method with the n-type impurity can be fully Merged into the general subquarter-micron CMOS processes.
Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution
(2002)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電機學院
;
College of Electrical and Computer Engineering
Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs
(2002-06-01)
Ker, MD
;
Peng, JJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
During manufacture of wire bonding in packaged IC products, the breaking of bond wires and the peeling of bond pads occur frequently. The result is open-circuit failure in IC products. There were several prior methods reported to overcome these problems by using additional process flows or special materials. In this paper, a layout method is proposed to improve the bond wire reliability in general CMOS processes. By changing the layout patterns of bond pads, the reliability of bond wires on bond pads can be improved. A set of different layout patterns of bond pads has been drawn and fabricated in a 0.6-mum single-poly triple-metal CMOS process for investigation by the bond wire reliability tests, the ball shear test and the wire pull test. By implementing effective layout patterns on bond pads in packaged IC products, not only the bond wire reliability can be improved, but also the bond pad capacitance can be reduced for high frequency application. The proposed layout method for bond pad design is fully process-compatible to general CMOS processes.
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
(2002)
Peng, JJ
;
Ker, MD
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a bulk CMOS chip, the core circuit blocks are always latchup sensitive due to a low holding voltage of the parasitic SCR path. The proposed latchup prevention methodology and circuit design can detect and stop the occurrence of latchup without any process modification or extra fabrication cost. It is suitable for whole-chip latchup prevention of bulk CMOS integrated circuits. This proposed latchup current self-stop methodology and circuit have been verified in a 0.5-mum 1P3M bulk CMOS process.
Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
(2002-11-15)
Ker, MD
;
Hsu, HC
;
Peng, JJ
;
電機學院
;
College of Electrical and Computer Engineering
A novel ion implantation method for electrostatic discharge protection, often called as ESD implantation, is proposed to significantly improve machine-model (MM) ESD robustness of N-channel metal-oxide semiconductors (NMOS) device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L = 300 mum/0.5 mum for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25-mum complementary metal-oxide semiconductors (CMOS) process.
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's
(2003)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電機學院
;
College of Electrical and Computer Engineering
For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-mum 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.