Browsing by Author "Peng, Kang-Ping"

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A novel solution for efficient in situ TEM cross-section and plan-view analyses with an advanced sample preparation scheme
(2018-01-01)
Peng, Kang-Ping
;
Hsu, Kim
;
Ger, Finn
;
Tsai, Tsung-Chang
;
電子工程學系及電子研究所
A novel approach for failure analysis with in situ TEM method is proposed and demonstrated in this work. With an ingenious sample preparation scheme, the approach allows us to perform both plan-view and cross-sectional TEM inspections on the same failure sites in a chip in an efficient way. The sample preparation is not difficult and can be processed with conventional tools. In the beginning, a large-area lamella for plane-view analysis is prepared and the condition of the SEM inspection is appropriately adjusted to enhance the voltage contrast revealed by the failure sites. Then the lamella is further processed by means of FIB milling to enable further examination with the cross-sectional TEM. As compared with the traditional way of preparing TEM P-V samples, this method can save time by more than 70%.
Coordinated and Simultaneous Formation of Paired Ge Quantum Dots by Thermal Oxidation of Designer Poly-SiGe Spacer Structures
(2020-01-01)
Chen, Han-Yu
;
Peng, Kang-Ping
;
George, Thomas
;
Lin, Horng-Chih
;
Li, Pei-Wen
We report a novel self-organized approach for the controllable placement of paired Ge quantum dots (QDs) along each sidewall edge of poly-Si ridges by simply thermally oxidizing spacer layers of poly-SiGe and Si3N4 that conformally encapsulate the poly-Si ridges. Additionally, controllable diameters ranging from 20-50 nm and precise location of paired Ge QDs are enabled by adjusting the thickness of poly-SiGe spacer layers in combination with specific processing conditions. These conditions include the subsequent lithographic patterning through direct etch-back for forming spacer stripes and spacer islands. The spacing between paired Ge QDs across the ridge is essentially determined by the width of the patterned poly-Si ridge. Inter-QD spacings along the sidewall of the poly-Si ridge are a consequence of heterogeneous nucleation and Ostwald Ripening.
Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel
(2018-04-01)
Chang, You-Tai
;
Peng, Kang-Ping
;
Li, Pei-Wen
;
Lin, Horng-Chih
;
電機學院
In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core. (C) 2018 The Japan Society of Applied Physics.
Feasibility of Ge double quantum dots with high symmetry and tunability in size and inter-dot spacing
(2019-01-01)
Peng, Kang-Ping
;
Huang, Tsung-Lin
;
George, Thomas
;
Lin, Horng-Chih
;
Li, Pei-Wen
We report the tunability of the sizes and inter-dot spacings of Ge coupled quantum dots (QDs) using nano-spacer technology in combination with selective oxidation of Si0.85Ge0.15. Spherical-shaped Ge QDs were formed at each sidewall corner of the nano-patterned Si3N4 ridges by thermal oxidation of poly-SiGe spacer layers encapsulating the Si3N4 nano-ridges. The diameters of the Ge spherical QDs are essentially determined by geometrical height, width, and length of the nano-spacer islands of poly-SiGe, which are tunable by adjusting the process times of their deposition and etch back. The inter-dot spacing between the Ge DQDs are controllable by adjusting the widths of the lithographically-patterned Si3N4 ridges and the thermal oxidation times. Our self-organization and self-alignment approach achieved high symmetry within the Ge DQDs in terms of the individual QD sizes as well as the coupling barriers between the QDs and external electrodes in close proximity.
Ge nanodot-mediated densification and crystallization of low-pressure chemical vapor deposited Si3N4 for advanced complementary metal-oxide-semiconductor photonics and electronics applications
(2019-10-04)
Peng, Kang-Ping
;
Huang, Tsung Lin
;
George, Tom
;
Lin, Horng-Chih
;
Li, Pei-Wen
A new phenomenon of highly localized, nanoscale densification and crystallization of silicon-nitride (Si3N4) layers has been observed. A drastic reduction in the thermal budget (temperature and processing time) for local densification and even nanocrystallization of low-pressure chemical vapor deposited amorphous Si3N4 layers is mediated by the presence of Ge, Si, and O interstitials in close proximity to the Si3N4. The enhancement of localized densification and nanocrystallization observed in Si3N4 layers appears to be catalyzed by proximal Ge quantum dots (QDs) 'migrating' through the Si3N4/Si layers and are influenced by the oxidation time and Ge QD size. Implications of the highly localized, nanoscale densification and crystallization of silicon-nitride (Si3N4) layers for photonic and electronic device applications are discussed.
Self-Organized Ge Nanospherical Gate/SiO2/Si0.15Ge0.85-Nanosheet n-FETs Featuring High ON-OFF Drain Current Ratio
(2019-01-01)
Liao, Po-Hsiang
;
Peng, Kang-Ping
;
Lin, Horng-Chih
;
George, Thomas
;
Li, Pei-Wen
We reported experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. This unique gate-stacking heterostructure is simultaneously produced in a single oxidation step as a consequence of an exquisitely controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials at 900 degrees C. Process-controlled tunability of nanospherical gate of 60-100 nm in diameter, gate oxide thickness of 3 nm, and Si0.15Ge0.85 nanosheet with compressive strain of -2.5% was achieved. Superior gate modulation is evidenced by subthreshold slope of 150 mV/dec and I-ON/I-OFF > 5 x 10(8) (I-OFF < 10(-6) mu A/mu m and I-ON > 500 mu A/mu m) measured at V-G = + 1V, V-D = + 1 V, and T = 80 K for our device with channel length of 75 nm.
Self-organized Pairs of Ge Double Quantum Dots with Tunable Sizes and Spacings Enable Room-Temperature Operation of Qubit and Single-Electron Devices
(2019-01-01)
Peng, Kang-Ping
;
Chen, Ching-Lun
;
Tang, Ying-Tsan
;
Kuo, David
;
George, Thomas
We report the first-of-its-kind, paired Ge double quantum dots (DQDs) using spacer technology in combination with selective oxidation of Si0 85Ge0 15 in a self-organization approach. Process-controlled tunability of the spherical Ge QD diameters (5-20nm) and inter-QD spacings as close as 12nm were achieved by thermal oxidation of poly-SiGe spacer islands at each sidewall corner of Si3N4/poly-Si ridges. Based on the capability of producing highly-symmetrical Ge DQDs in terms of QD sizes and the coupling barriers of thermal SiO2/densified Si3N4 between the QDs and proximal electrodes, we demonstrated room-temperature operation of Ge qubit devices, within which one QD encodes charges and the other QD-single-electron transistor (SET) senses and read-out the qubit. Theoretical analysis on the size-tunable density of states for Ge QDs and the tunneling paths in DQDs were conducted. Our Ge DQD system enables a practically achievable building block for QD qubit devices on Si platform.
Study on Random Telegraph Noise of Gate-All-Around Poly-Si Junctionless Nanowire Transistors
(2017-01-01)
Yang, Chen-Chen
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Peng, Kang-Ping
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Chen, Yung-Chen
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Lin, Horng-Chih
;
Li, Pei-Wen
In this work we study the random telegraph noise (RTN) characteristics of short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors. The test devices were fabricated with I-line-based lithography in combination with novel spacer-etching techniques for aggressively shrinking the channel dimension. Based on the tiny nanowire channel and short-channel length, we are able to detect clear RTN signals as the gate voltage is sufficiently large. Location of the trap responsible for the RTN is estimated to be 1.13 nm within the gate oxide away from the oxide/channel interface.
Study on random telegraph noise of high-idmetal-gate gate-all-around poly-Si nanowire transistors
(2020-04-01)
Chang, You-Tai
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Tsai, Yueh-Lin
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Peng, Kang-Ping
;
Su, Chun-Jung
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Li, Pei-Wen
In this Paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-kappa oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side. (C) 2020 The Japan Society of Applied Physics
The development of low-temperature atomic layer deposition of HfO2 for TEM sample preparation on soft photo-resist substrate
(2018-01-01)
Peng, Kang-Ping
;
Liu, Ya-Chi
;
Lin, I-Feng
;
Lin, Chih-Chien
;
Huang, Shu-Wei
In this study, the method of low-temperature atomic layer deposition (ALD), which is applied on the soft photo-resist (PR) substrate forming hafnium dioxide (HfO2) at 40 degrees C to 85 degrees C, is reported for the first time. This reveals the potential application in the TEM sample preparation. The thickness, refractive index, band gap, and depth profiling chemical state of the thin film are analyzed by ellipsometry, X-ray diffraction, and photoelectron spectroscopy respectively. Our TEM image shows a clear boundary between the photo-resist and hafnium dioxide deposited on PR, which indicates the low-temperature atomic layer deposition (ALD) may lead a new way for TEM sample preparation in advanced technology node.
The effects of channel doping concentration for n-type junction-less double-gate poly-Si nanostrip transistors
(2014-05-01)
Liu, Keng-Ming
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Peng, Fan-I
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Peng, Kang-Ping
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Lin, Horng-Chih
;
Huang, Tiao-Yuan
In this study, novel n-type double-gate (DG) junction-less (J-less) polycrystalline silicon (poly-Si) nanostrip transistors with different channel doping concentrations (N-C) have been fabricated and investigated. The effects of channel doping concentration on device characteristics were examined comprehensively in this work. The experimental data show that as the channel doping concentration of the J-less device increases, the threshold voltage (V-TH) becomes more negative. Besides, the drain-induced barrier lowering and the subthreshold swing of the J-less transistors become larger as the channel doping increases. We also found that as the channel doping increases, the off-current (I-OFF) increases and the on-current (I-ON) actually decreases due to the doping-dependent mobility degradation. The conduction mechanisms under different channel doping concentrations were also investigated by TCAD simulation. The experimental results suggest that the n-type DG nanostrip J-less transistor with lower channel doping will have superior device characteristics.
The Germanium "Halo": Visualizing Ge interstitial dynamics in nanocrystallite formation
(2018-10-01)
George, Thomas
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Huang, Tsung-Lin
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Hsueh, Chui-Yu
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Peng, Kang-Ping
;
Lin, Horng-Chih
We report the ability to image distributions of Ge interstitials within amorphous SiO2 matrices using conventional transmission electron microscopy and energy dispersive X-ray spectroscopy mapping. While previous, established methods have only been able to indirectly infer the presence of interstitials within materials, our direct "visualization" approach allows the ability to study and better understand the dynamics of several interesting phenomena occurring within the Ge-Si-O system during processing at temperatures greater than 700 degrees C which has not been described in any previously published work. Experimental observations by TEM of the Ge interstitial dynamics has allowed us to clarify the various operating mechanisms for Ge nanocrystallite growth within these SiO2 matrices. These phenomena include Ostwald ripening, migration of Ge nanocrystallites through amorphous SiO2 and Si3N4 matrices, Ge incorporation in Si-rich materials such as Si3N4 and Si, and finally, morphological changes in the Ge nanocrystallites themselves. (c) 2018 The Japan Society of Applied Physics.
Trapping Depth and Transition Probability of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor
(2020-01-01)
Change, You-Tai
;
Tsai, Yueh-Lin
;
Peng, Kang-Ping
;
Su, Chun-Jung
;
Li, Pei-Wen
In this article, we investigate the four-level random telegraph noise (RTN) characteristics of a gate-all-around (GAA) nanowire (NW) transistor. The RTN-testing devices were fabricated with the sidewall spacer etching technique. The effective channel length and width are approximately 150 and 30 nm, respectively. By decoupling the four-level RTN, we are able to extract the time constants associated with the two traps. Circle-shaped approximations are used to mimic the triangular NW for evaluating the depths of the traps. The extracted depths of the two traps are very close to each other, which is consistent with the time-evolution measured results. We've also explored the probabilities of transitions between two specific current levels in the RTN characteristics, as well as the relative trapping/de-trapping frequencies.
Tunable diameter and spacing of double Ge quantum dots using highly-controllable spacers and selective oxidation of SiGe
(2019-08-05)
Huang, Tsung-Lin
;
Peng, Kang-Ping
;
Chen, Ching-Lun
;
Lin, Horng-Chih
;
George, Tom
We report the novel tunability of the diameters and spacings of paired Ge double quantum dots (DQDs) using nano-spacer technology in combination with selective oxidation of Si0.85Ge0.15 at high temperature. Pairs of spherical-shaped Ge QDs were formed by the selective oxidation of poly-SiGe spacer islands at each sidewall corner of the nano-patterned Si3N4/poly-Si ridges. The diameters of the Ge spherical QDs are essentially determined by geometrical conditions (height, width, and length) of the nano-patterned spacer islands of poly-SiGe, which are tunable by adjusting the process times of deposition and etch back for poly-SiGe spacer layers in combination with the exposure dose of electron-beam lithography. Most importantly, the separations between the Ge DQDs are controllable by adjusting the widths of the poly-Si/Si3N4 ridges and the thermal oxidation times. Our self-organization and self-alignment approach achieved high symmetry within the Ge DQDs in terms of the individual QD diameters as well as the coupling barriers between the QDs and external electrodes in close proximity.
ZnON Contacts Enabling High-performance 3-D InGaZnO Inverters
(2018-01-01)
Kuan, Chin-I
;
Peng, Kang-Ping
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
電子工程學系及電子研究所
The inclusion of an ultra-thin zinc oxynitride (ZnON) layer inserted between the channel of InGaZnO (IGZO) and source/drain (S/D) metal of Al for an IGZO thin-film transistor (TFT) is demonstrated to improve device performance in terms of a reduction in S/D series resistance (RSD). The improvement is attributable to the elimination of an interfacial layer of AlOx which is inherently formed at the Al/IGZO interface, by the insertion of ZnON. Characteristics of 3D stacked-type inverters constructed by the IGZO TFTs with ZnON contacts have been also studied. Full-swing switching with voltage gains increases from 9.8V/V for the IGZO inverter without ZnON contacts to 12.3 V/V with ZnON contacts at an operating voltage of 5 V.