Browsing by Author "Peng, WH"

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A low complexity prioritized bit-plane coding for SNR scalability in MPEG-21 scalable video coding
(2005)
Peng, WH
;
Chiang, TH
;
Hang, HM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a low complexity prioritized bit-plane coding scheme to improve the rate-distortion performance of cyclical block coding in MPEG-21 scalable video coding. Specifically, we use a block priority assignment algorithm to firstly transmit the symbols and the blocks with potentially better rate-distortion performance. Different blocks are allowed to be coded unequally in a coding cycle. To avoid transmitting priority overhead, the encoder and the decoder refer to the same context to assign priority. Furthermore, to reduce the complexity, the priority assignment is done by a look-up-table and the coding of each block is controlled by a simple threshold comparison mechanism. Experimental results show that our prioritized bit-plane coding scheme can offer up to 0.5dB PSNR improvement over the cyclical block coding described in the joint scalable verification model (JSVM).
A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC
(2005-02-01)
Chang, SC
;
Peng, WH
;
Wang, SH
;
Chiang, T
;
電子工程學系及電子研究所
In this paper, we proposed a platform based bus-interleaved architecture for the de-blocking filter in H.264. Specifically, to efficiently use the bus bandwidth, we classify the filtering mode into 8 types and use an adaptive transmission scheme to avoid redundant data transfer. Moreover, to reduce the processing latency, we use a bus-interleaved architecture for conducting data transmission and filtering in parallel. As compared to the state-of-the-art designs, our scheme offers 1.6x to 7x performance improvement. While clocking at 100MHz, our design can support 2560x1280@30Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can be easily applied in system-on-chip design.
A platform-based de-blocking filter design with bus-interleaved architecture for H.264
(2005)
Chang, SC
;
Peng, WH
;
Wang, SH
;
Chiang, TH
;
交大名義發表
In this paper, we present an ARM platform-based architecture design for de-blocking filter in H.264. According to statistical analysis, we propose an adaptive transmission scheme to reduce the bus workload. Moreover, we develop a bus-interleaved architecture to reduce the processing latency. As compared to the state-of-the-art designs, our scheme offers 3x to 14x performance improvement. Furthermore, we have proved our design using an ARM emulation board.
A platform-based MPEG-4 Advanced Video Coding (AVC) decoder with block level pipelining
(2003)
Wang, SH
;
Peng, WH
;
He, YW
;
Lin, GY
;
Lin, CY
We present a baseline MPEG-4 AVC (Advanced Video Coding) decoder based on an optimized platform-based design methodology. With this methodology, we jointly optimize the software and hardware design of the decoder. Overall decoding throughput is increased by synchronizing the software and the dedicated co-processors. The synchronization is achieved at macroblock-level pipelining. In addition, we optimize the decoder software by enhancing the frame buffer management, boundary padding, and content aware inverse transform. To speed up motion compensation and inverse transform, which are the most computationally intensive modules, two dedicated acceleration modules are realized. For comparison, the proposed prototype decoder and MPEG-4 AVC reference decoder are evaluated on an ARM platform, which is one of most popular portable devices. Our experiments show that the throughput of the MPEG-4 reference decoder can be improved by 6 to 7 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5 frames per second (fps) for QCIF video sequences. With the dedicated accelerators, the overall throughput is increased by about 30% to reach 6.6 fps on the average and is up to 10.3 fps for slow motion video sequences.
A prioritized end-to-end video streaming scheme using MPEG-4 fine granularity scalability
(2002)
Peng, WH
;
Chiang, TH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a new client buffer management scheme to adaptively regulate and optimize the decoded video quality for video streaming applications. Our scheme packetizes and prioritizes the video bitstream of MPEG-4 Fine Granularity Scalability. We assign individual packet a priority factor according to its rate-distortion performance and the buffer is managed based on the received aggregate priority factor for each frame. Since the packetization process considers the priority, our algorithm can use such information to perform real-time packets/bits allocation at the client buffer. For a given available bandwidth and constrained processing power, we provide improved performance in terms of reduction of visual quality variation and enhancement of overall visual quality.
A software-hardware co-implementation of MPEG-4 Advanced Video Coding (AVC) decoder with block level pipelining
(2005-08-01)
Wang, SH
;
Peng, WH
;
He, YW
;
Lin, GY
;
Lin, CY
We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.
Advances of MPEG scalable video coding standard
(2005)
Peng, WH
;
Tsai, CY
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Chiang, TH
;
Hang, HM
;
交大名義發表
To support clients with diverse capabilities, the MPEG committee is defining a novel scalable video coding (SVC) framework that can simultaneously support multiple spatial, temporal and SNR resolutions under the constraints of low complexity and low delay. To fulfill the requirements, two major approaches have been considered as the potential technologies. One is the wavelet-based scheme and the other is the scalable extension of MPEG-4 AVC/H.264. This paper aims to give a brief overview for the latest advances of these technologies.
Context-based binary arithmetic coding for fine granuality scalability
(2003)
Peng, WH
;
Chiang, TH
;
Hang, HM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We proposed a context-based binary arithmetic coding to improve entropy coding of the enhancement layer for the H.26L-, based Fine Granularity Scalability (FGS). Instead of independent bit-plane coding, we exploit correlation between various bit-planes and neighboring coefficients. For each bit-plane, we perform significant/refinement bit partition and construct contexts separately in terms of energy clustering and distribution of DCT coefficients. For the significant bit, we extend one-dimensional run-length coding to multiple dimensions and segment the significant bit-planes. For the refinement bit, we put together refinement bits exhibiting stronger correlation by energy groups and apply run-length coding distinctively. Particularly, we introduce the maximum run concept to offer better statistical adaptation. Averagely, our approach reduces the enhancement-layer bit stream by 7similar to8% and improves the PSNR by 0.3similar to0.5dB. Moreover, our performance outperforms the JPEG-2000 for the encoding of the enhancement layer.
Context-based binary arithmetic coding with stochastic bit reshuffling for advanced Fine Granuality Scalability
(2004)
Peng, WH
;
Wang, CN
;
Chiang, TH
;
Hang, HM
;
交大名義發表
We present a novel context based binary arithmetic coding with a stochastic bit-reshuffling scheme to improve bit-plane coding of MPEG-4 Fine Granularity Scalability (FGS). Current approach has not fully considered the correlations across bit-planes and among adjacent transform blocks. To fully exploit correlation, we construct context based on spatial correlation and energy distribution of transform blocks. Furthermore, we consider the context across bit-planes to reduce side information. In addition. when the enhancement-layer is partially decoded, the block update in a raster scan causes unbalanced quality of a decoded frame. To have consistent subjective quality, we reshuffle the bit transmission order with a probability model. Since both encoder and decoder have identical probability model, no extra overhead are required. For faster convergence of statistic adaptation.. we replace the traditional 8 x 8 floating point DCT with 4 x 4 integer transform. As compared to MPEG-4 FGS based bit-plane coding, we can improve the PSNR by 0.5similar to1dB and offer better subjective quality. Specifically, our approach is among top 3 of the Test 1(b) and 1(c) in the subjective quality evaluation of scalable video coding in the 65th MPEG meeting in July 2003.
Enhanced mode-adaptive fine granularity scalability
(2003)
Peng, WH
;
Chen, YK
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this article, we present a scalable video compression algorithm to deliver higher compression efficiency with limited drifting error. MPEG-4 Fine Granularity Scalability (FGS) compresses the video into a base layer and an enhancement layer. Currently, because the enhancement layer is predicted from the poor-quality base layer, the compression efficiency is low. To improve the compression efficiency, we construct enhancement-layer predictors from (1) macroblocks of current reconstructed base-layer frame, (2) macroblocks of previously reconstructed enhancement-layer frame, and (3) the average of previous two. On the other hand, the unpredictable receiving manner of enhancement layer could cause predictor mismatch error. The predictor mismatch error further results in drifting error. To minimize the drifting error, we create an adaptive mode-selection algorithm, in the encoder, which first smartly estimates possible drifting error of the decoder side and then uses the best macroblock modes wisely. In this article, we show that predictors constructed jointly from the base-layer frame and the enhancement-layer frame can reduce the drifting error. And, predictors constructed from the base-layer frame can stop the drifting error. As compared to other advance FGS schemes, our algorithm shows 0.3-0.5 dB PSNR improvement with a less complex structure. Although compared to MPEG-4 FGS, more than 1-1.5 dB quality improvement can be gained. (C) 2004 Wiley Periodicals, Inc.
Enhanced stochastic bit reshuffling for fine granular scalable video coding
(2004)
Peng, WH
;
Chiang, TH
;
Hang, HM
;
Lee, CY
;
交大名義發表
In this paper, we propose an enhanced stochastic bit reshuffling (SBR) scheme to deliver better subjective quality for fine granular scalable (FGS) video coding. Traditional bit-plane coding in FGS algorithm suffers from poor subjective quality due to zigzag and raster scanning order. To tackle this problem, our SBR rearranges the transmission order of each bit by its estimated rate-distortion performance. Particularly, we model the transform coefficient with a maximum likelihood based Laplacian distribution and incorporate it into the context probability model for content-aware parameter estimation. Moreover, we use a dynamic priority management scheme for the SBR. Experimental results show that our enhanced SBR together with context adaptive binary arithmetic coding offers up to 1.5dB PSNR improvement and shows better visual quality as compared to the scheme in MPEG-4 FGS.
Platform based design of all binary motion estimation (ABME) with bus interleaved architecture
(2005)
Wang, SH
;
Tao, WL
;
Wang, CN
;
Peng, WH
;
Chiang, T
This paper presents an efficient hardware-software implementation with a marcoblock based pipelining and a bus interlaced architecture for all binary motion estimation (ABME), which has been proven to be simple and low cost for hardware design. The bus interleaved preprocessing module of the ABME architecture can generate downsampling and binarized data in the same flow without additional dedicated hardware. With the 3-layer binary bitplane of ABME, we use a two-dimensional (2-D) mapping unit and a binary adder tree instead of a systolic array to compute the block matching metric, which is sum of difference (SoD), in one cycle. In addition, a new bus bandwidth reduction scheme is proposed by reusing the binarized image, which can achieve up to 67% bus bandwidth saving. The experiment shows that for each macroblock, our design can finish ABME within 283 cycles with 65k gate counts synthesized by UMC 0.18 um cell library.