Browsing by Author "Peng, Yin-Chi"

Now showing 1 - 9 of 9

A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata
(2017-12-01)
Tsai, Hsiang-Jen
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Chen, Chien-Chih
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Peng, Yin-Chi
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Tsao, Ya-Han
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Chiang, Yen-Ning
Regular expression matching becomes indispensable elements of Internet of Things network security. However, traditional ternary content addressable memory (TCAM) search engine is unable to handle patterns with wildcards, as it precisely tracks only one active state with single transition. This paper proposes a promising simultaneous pattern matching methodology for wildcard patterns by two separated engines to represent discrete finite automata. A key preprocessing to encode possible postfix pattern by a unique key ensures that follow-up patterns can accurately traverse all possible matches with limited hardware resources. This approach is practical and scalable for achieving good performance and low space consumption in network security, and it can be applicable to any regular expressions even with multiwildcard patterns. The experimental results demonstrate that this scheme can efficiently and accurately recognize wildcard patterns by simultaneously tracking only two active states. By adopting SRAM TCAM in the proposed architecture, the energy consumption is reduced to around 39%, compared with the energy consumption using a computing system that contains a large memory lookup and comparison overhead.
Adaptive Granularity and Coordinated Management for Timely Prefetching in Multi-Core Systems
(2015)
Chang, Chia-Jung
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Peng, Yin-Chi
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Chen, Chien-Chih
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Chen, Tien-Fu
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Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetching to improve the system performance. However, untimely prefetching may pollution caches and resulting into significant performance degradation. In this work, we introduce an Adaptive Granularity and coordinated Prefetching (AGP) that consists of a coarse-grained and fine-grained prefetched mechanism to provide a better caching environment for parallel applications. AGP targets on the degree-adjusting and location-choosing and tries to minimize the influence caused by prefetcher for each core. AGP could produce more timely prefetched requests reducing the cache pollutions and contentions. Across a variety of PARSEC benchmarks, AGP can contribute 6.5% (up to 36%) of performance improvement on a 4-core multicore system compared to the non-prefetching.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013)
Peng, Yin-Chi
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Chen, Chien-Chih
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Chang, Chia-Jung
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Chen, Tien-Fu
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Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013-01-01)
Peng, Yin-Chi
;
Chen, Chien-Chih
;
Chang, Chia-Jung
;
Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.
DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation
(2014-01-01)
Chen, Chien-Chih
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Peng, Yin-Chi
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Chen, Cheng-Fen
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Wu, Wei-Shan
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Min, Qinghao
Faced with increasingly large multicore chip designs, architects need fast and accurate simulations for their exploration of design spaces within a limited simulation time budget. In multithreaded applications, threads cannot run simultaneously. Sampling is commonly used to reduce simulation time, but conventional sampling barely detects the instantaneous program variations of synchronization events and the inconsistency between phases of each core. This work proposes a dynamic adjustment and partial sampling technique (DAPs), consisting of aggressive sampling, lazy sampling, and regular sampling, to overcome thread interference in multithreaded applications. Moreover, DAPs partially selects sampling cores to reduce the overhead of sampling inconsistent phases.
Energy- Efficient TCAM Search Engine Design Using Priority- Decision in Memory Technology
(2017-03)
Tsai, Hsiang-Jen
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Yang, Keng-Hao
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Peng, Yin-Chi
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Lin, Chien-Chen
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Tsao, Ya-Han
Ternary content-addressable memory (TCAM)-based search engines generally need a priority encoder (PE) to select the highest priority match entry for resolving the multiple match problem due to the don\'t care (X) features of TCAM. In contemporary network security, TCAM-based search engines are widely used in regular expression matching across multiple packets to protect against attacks, such as by viruses and spam. However, the use of PE results in increased energy consumption for pattern updates and search operations. Instead of using PEs to determine the match, our solution is a three-phase search operation that utilizes the length information of the matched patterns to decide the longest pattern match data. This paper proposes a promising memory technology called priority-decision in memory (PDM), which eliminates the need for PEs and removes restrictions on ordering, implying that patterns can be stored in an arbitrary order without sorting their lengths. Moreover, we present a sequential input-state (SIS) scheme to disable the mass of redundant search operations in state segments on the basis of an analysis distribution of hex signatures in a virus database. Experimental results demonstrate that the PDM-based technology can improve update energy consumption of nonvolatile TCAM (nvTCAM) search engines by 36%-67%, because most of the energy in these search engines is used to reorder. By adopting the SIS-based method to avoid unnecessary search operations in a TCAM array, the search energy reduction is around 64% of nvTCAM search engines.
Energy-Efficient Non-Volatile TCAM Search Engine Design Using Priority-Decision in Memory Technology for DPI
(2015)
Tsai, Hsiang-Jen
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Yang, Keng-Hao
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Peng, Yin-Chi
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Lin, Chien-Chen
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Tsao, Ya-Han
TCAM-based search engines are widely used in regular expression matching across multiple packets. However, the use of priority encoder results in increased energy consumption of pattern updates and search operations. This work, proposes a promising memory technology, called Priority-Decision in Memory (PDM), which eliminates the need for priority encoders and removes restrictions on ordering, meaning that patterns can be stored in an arbitrary order without sorting their lengths. Moreover, we present a Sequential Input-State Search (SIS) scheme to disable the mass of redundant search operations in state segments, based on the analysis distribution of hex signatures in a virus database. Experimental results demonstrate that PDM-based technology can improve update energy consumption of nvTCAM search engines by 36%similar to 67% because most of the energy in the latter is used to reorder. By adopting the SIS-based method to avoid unnecessarily search operations in a TCAM array, the search energy reduction is around 64% of nvTCAM search engines.
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control
(2017-05-01)
Peng, Yin-Chi
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Chen, Chien-Chih
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Tsai, Hsiang-Jen
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Yang, Keng-Hao
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Huang, Pei-Zhe
To alleviate high energy dissipation of unnecessary snooping accesses, snoop filters have been designed to reduce snoop lookups. These filters have the problem of decreasing filtering efficiency, and thus usually rely on partial or whole filter reset by detecting block evictions. Unfortunately, the reset conditions occur infrequently or unevenly (called passive filter deletion). This work proposes the concept of revitalized snoop filter (RSF) design, which can actively renew the destination filter by employing a generation wrapping-around scheme for various reference behaviors. We further utilize a sampling mechanism for RSF to timely trigger precise filter revitalizations, so that unnecessary RSF flushing can be minimized. The proposed RSF can be integrated to various existent inclusive snoop filters with only a minor change to their designs. We evaluate our proposed design and demonstrate that RSF eliminates 58.6% of snoop energy compared to JETTY on average while inducing only 6.5% of revitalization energy overhead. In addition, RSF eliminates 45.5% of snoop energy compared to stream registers on average and only induces 2.5% of revitalization energy overhead. Overall, these RSFs reduce the total L2 cache energy consumption by 52.1% (58.6% - 6.5%) as compared to JETTY and by 43% (45.5% - 2.5%) as compared to stream registers. Furthermore, RSF improves the overall performance by 1% to 1.4% on average compared to JETTY and stream registers for various benchmark suites.
Lifetime-aware LRU Promotion Policy for Last-level Cache
(2015)
Wu, Hong-Yi
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Chen, Chien-Chih
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Tsai, Hsiang-Jen
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Peng, Yin-Chi
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Chen, Tien-Fu
The traditional LRU replacement policy is susceptible to memory-intensive workloads with large non-reused data like thrashing applications and scan applications. For such workloads, the majority of cache blocks don\'t get any cache hits during residing in the cache. Cache performance can be improved by reducing the interference from non-reused data. Therefore, the lifetime of other blocks is increased and it can contribute to cache hit. We propose a Lifetime-aware LRU Promotion Policy and show that changing the promotion policy can effective reduce cache miss in the last-level cache. Our promotion policy dynamically adjusts promotion strategy and increases the lifetime for useful cache blocks. The experimental results show that our proposal reduces the average MPKI by 6% and 9% over EAF and DIP, respectively. In multicore, we also improve the performance and reduce the MPKI.