Browsing by Author "Rao, P. -Z."

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Low-power VCO with phase-noise improvement in 0.18 mu m CMOS technology
(2010-09-30)
Liang, C. -P.
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Huang, T. -J.
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Rao, P. -Z.
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Chung, S. -J.
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傳播研究所
A low-power 5.25 GHz voltage-controlled oscillator ( VCO) with phase-noise improvement is designed in a 0.18 mu m CMOS 1P6M process. Owing to the use of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of transistor, a good figure of merit of - 190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a core power consumption of 1.9 mW and active chip area of 0.15 mm(2). The measured phase noise at 1 MHz offset is about - 119 dBc/Hz.
Quadrature current-reused divide-by-3 semi-dynamic frequency divider with active balun
(2012-01-05)
Lin, C. -Y.
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Rao, P. -Z.
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Lin, Y. -K.
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Chung, S. -J.
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傳播研究所
A divide-by-3 semi-dynamic frequency divider (SDFD) with active balun is presented using the current-reused technique. The proposed SDFD is composed of a Gilbert cell mixer, one stage of static divider and an active balun. The LO switching stage of the Gilbert cell mixer is also the current source of the static frequency divider to construct the current-reused architecture. At the incident power of 0 dBm, this frequency divider operates at the maximum bandwidth of 1100 MHz from 21.5 to 22.6 GHz. The power consumption of the divider is 12 mW at a 1.5 V supply voltage.