Browsing by Author "Reck, Theodore J."

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A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
(2016-12-01)
Zhao, Yan
;
Chen, Zuow-Zun
;
Du, Yuan
;
Li, Yilei
;
Al Hadi, Richard
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
(2016-12)
Zhao, Yan
;
Chen, Zuow-Zun
;
Du, Yuan
;
Li, Yilei
;
Al Hadi, Richard
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
Integrated Wide-Band CMOS Spectrometer Systems for Spaceborne Telescopic Sensing
(2019-05-01)
Zhang, Yan
;
Kim, Yanghyo
;
Tang, Adrian
;
Kawamura, Jonathan H.
;
Reck, Theodore J.
For spaceborne instrumentation, the prohibitive cost of a flight traditionally favors programmable solutions such as field programmable gate arrays (FPGAs). As scientific goals become more ambitious, the FPGA-based solutions are showing limitations, especially with restricted launch vehicle capacity and available solar power. In this paper, modern integrated circuit technology is adopted to realize two fully integrated spectrometer SoCs to support spaceborne telescopic sensing. The system specifications are derived from the scientific principles of radio-frequency spectroscopy while each component strives for a simple and reliable implementation. Realized in 65-nm CMOS technology, Design A operates at 2.6 GHz with a three-bit ADC, a 2048-point FFT with 8192-point polyphase filter bank, and a billion-count accumulator. Design B more than doubles the bandwidth, reaches 6 GS/s by interleaving the ADC. The FFT size is also quadrupled to 8192. Both designs include integrated phase locked loops and tunable clock distribution networks. Design A consumes a peak power of 650 mW and Design B consumes 1.5 W. They represent the highest level of integration among similar endeavors and achieve orders of magnitude of improvement over traditional solutions in terms of size, weight, and power consumption. Both designs are actively involved in NASA's spectroscopy missions.