Browsing by Author "SHEN, WZ"

Now showing 1 - 16 of 16

A CELL-BASED POWER ESTIMATION IN CMOS COMBINATIONAL CIRCUITS
(1994)
LIN, JY
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LIU, TC
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SHEN, WZ
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
AN ANALYTICAL MODEL FOR HIGH-LOW-EMITTER (HLE) SOLAR-CELLS IN CONCENTRATED SUNLIGHT
(1981)
SHEN, WZ
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WU, CY
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交大名義發表
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電控工程研究所
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National Chiao Tung University
CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTS
(1989-12-07)
CHEN, JE
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LEE, CL
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SHEN, WZ
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交大名義發表
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電控工程研究所
DESIGN OF PSEUDOEXHAUSTIVE TESTABLE PLA WITH LOW OVERHEAD
(1993-07-01)
SHEN, WZ
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HWANG, GH
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HSU, WJ
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JAN, YJ
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電控工程研究所
The pseudoexhaustive testing (PET) scheme is a economic approach to test a large embedded programmable logic array (PIA). In this paper, we propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying our algorithm, both the area overhead and test length are reduced significantly.
EFFICIENT OUTPUT PHASE ASSIGNMENT ALGORITHM FOR PLAS
(1993-10-01)
HSU, WJ
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SHEN, WZ
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電控工程研究所
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Institute of Electrical and Control Engineering
To implement a multiple output function, one has the option to realise each output with either true logic or complementary logic following with an inverter. In this paper, we propose an efficient algorithm to solve this output phase assignment problem for PLA implementation. Instead of using the double-phase cover minimisation approach, we use a property-checking procedure to estimate the cost of assignments. With the estimated costs, an assignment with minimum cost is chosen. The experimental results show that the proposed algorithm can obtain excellent assignment compared with other approaches.
EMOTA - AN EVENT-DRIVEN MOS TIMING SIMULATOR FOR VLSI CIRCUITS
(1990-08-01)
SHEN, WZ
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JOU, SJ
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TAO, YS
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交大名義發表
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電子工程學系及電子研究所
EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATOR
(1993-02-01)
JOU, SJ
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CHIOU, SH
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TAO, YS
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SHEN, WZ
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電控工程研究所
An efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC. is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space. signal and time simulation techniques. the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multiprocessor system.
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
(1995)
SHEN, WZ
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HUANG, JD
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CHAO, SM
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
MOTA - A MOSFET TIMING SIMULATOR
(1986-10-01)
JOU, SJ
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JEN, CW
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SHEN, WZ
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LEE, CL
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交大名義發表
MY-BOX REPRESENTATION FOR FAULTY CMOS CIRCUITS
(1990-06-01)
CHEN, JE
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LEE, CL
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SHEN, WZ
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交大名義發表
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電控工程研究所
ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN
(1994)
SHEN, WZ
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TAO, YH
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DUNG, LR
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
RESTRUCTURING AND LOGIC MINIMIZATION FOR TESTABLE PLA
(1993-04-01)
HWANG, GH
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SHEN, WZ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Based on the testable design techniques proposed in [12], [13], we first derive a testability measure named UCP (Untestability Cube-number Product) which can accurately indicate the extra logic needed in testable PLA. Using UCP as a cost function, we have developed two new algorithms. The first one is a restructuring algorithm named REST, and the other is a logic minimizer for testable PLA named LMTPLA. REST can not only restructure a minimized PLA and improve its UCP, but also preserve the same logic function and almost the same chip area simultaneously. Thus, we can make the restructured PLA testable by taking less extra hardware. In order to get a minimum UCP, two new techniques are proposed: 1) Cube-Reduction, and 2) Cube-Partition. Using Cube-Reduction, we can make cubes far from the primes and increases the testability. By Cube-Partition, we may find out those hard-to-test cubes and partition them into smaller but easier-to-test cubes. LMTPLA is principally based on ESPRESSO-II and REST. Different from other logic minimizers, it can consider the testability at the logic minimization process. In order to minimize UCP as well as the number of product terms, four strategies are developed: 1) deleting the cubes with poor testability and reserving the cubes with good testability, 2) giving up the primes, 3) if necessary, partitioning the more untestable cubes into smaller cubes, and 4) deleting the procedures which are useless in LMTPLA. REST and LMTPLA have been implemented on SUN4/260 in C language. For 40 benchmark circuits, the hardware overheads required are reduced by about 30-40%.
SEESIM - A FAST SYNCHRONOUS SEQUENTIAL-CIRCUIT FAULT SIMULATOR WITH SINGLE-EVENT EQUIVALENCE
(1993-04-01)
WU, CP
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LEE, CL
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SHEN, WZ
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.
SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT
(1987-12-01)
JOU, SJ
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SHEN, WZ
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JEN, CW
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LEE, CL
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交大名義發表
SINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITS
(1991-12-01)
CHEN, JE
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LEE, CL
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SHEN, WZ
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper studies single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults. This procedure has been applied to collapse faults for 31 benchmark sequential circuits [1] and the number of faults has collapsed to 43% of the original number.
THE OPEN-CIRCUIT VOLTAGE OF BACK-SURFACE-FIELD (BSF) P-N-JUNCTION SOLAR-CELLS IN CONCENTRATED SUNLIGHT
(1980)
WU, CY
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SHEN, WZ
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電控工程研究所
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奈米中心
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Institute of Electrical and Control Engineering