Browsing by Author "SHEU, ML"

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SIMPLIFYING SEQUENTIAL-CIRCUIT TEST-GENERATION
(1994-09-01)
SHEU, ML
;
LEE, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Design for testability reduces testing costs for sequential circuits. The authors present a parity checker DFT scheme they have incorporated into a finite-state machine synthesis system. Generating tests for circuits synthesized according to this scheme becomes extremely simple. The derived test sequence very efficiently detects faults.