Browsing by Author "SHIAU, YH"

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ADOPTABILITY AND EFFECTIVENESS OF MICROCODE COMPACTION ALGORITHMS IN SUPERSCALAR PROCESSING
(1992-05-01)
SHIAU, YH
;
CHUNG, CP
;
交大名義發表
;
資訊科學與工程研究所
;
National Chiao Tung University
Superscalar processing is a technique to improve uniprocessor performance by exploiting instruction-level parallelism to issue and execute more than one instruction per clock cycle. To achieve high performance, the instruction sequence must be arranged so that the maximum instruction-level parallelism and hence the minimum execution time are achieved. Microcode compaction is an essential task in the compilation of high-level language programs into microprograms. Four algorithms are widely used in microcode compaction: the first-come-first-served algorithm, critical path algorithm, branch and bound algorithm, and list scheduling algorithm. The objective of this research is to study the adaptability and effectiveness, and to modify the four algorithms so that they can be applied to the instruction scheduling in a basic block of superscalar processor systems to minimize the execution time of a program. Experiments are conducted to examine the adaptability and effectiveness of each algorithm.
BENCHMARKING AND ANALYSIS OF SUPERSCALAR ARCHITECTURE
(1994-03-01)
SHIAU, YH
;
CHUNG, CP
;
資訊科學與工程研究所
;
Institute of Computer Science and Engineering
Superscalar processing can improve the performance of a single CPU beyond that of traditional RISC machines by exploiting instruction-level parallelism. It is the objective of this study to design a superscalar system which will best exploit a given program's instruction-level parallelism. Three different architectural models, XPCB, XXPB, and X4P2, are used as vehicles in evaluating system performance and the degree of utilization of each individual functional unit. The XPCB model is used as a preliminary model to analyze the loading breakdowns of the various function types. It was found that the performance improvement of the XPCB model relative to a single-instruction stream model is only about 4.3 percent. In addition, the fixed-point operations are in great demand, and dominate the behavior as well as performance of the processor. Two enhanced models, the XXPB and the X4P2, are suggested to improve on the performance of the XPCB model by distributing fixed-point, and even floating-point operation loads among multiple functional units of the same type(s). Simulations show that the XXPB and X4P2 models can improve the performance of the sequential model by 50.8 and 61.6 percent, respectively.
BENCHMARKING AND ANALYSIS OF SUPERSCALAR ARCHITECTURE
(1994-03-01)
SHIAU, YH
;
CHUNG, CP
;
資訊科學與工程研究所
;
Institute of Computer Science and Engineering
Superscalar processing can improve the performance of a single CPU beyond that of traditional RISC machines by exploiting instruction-level parallelism. It is the objective of this study to design a superscalar system which will best exploit a given program's instruction-level parallelism. Three different architectural models, XPCB, XXPB, and X4P2, are used as vehicles in evaluating system performance and the degree of utilization of each individual functional unit. The XPCB model is used as a preliminary model to analyze the loading breakdowns of the various function types. It was found that the performance improvement of the XPCB model relative to a single-instruction stream model is only about 4.3 percent. In addition, the fixed-point operations are in great demand, and dominate the behavior as well as performance of the processor. Two enhanced models, the XXPB and the X4P2, are suggested to improve on the performance of the XPCB model by distributing fixed-point, and even floating-point operation loads among multiple functional units of the same type(s). Simulations show that the XXPB and X4P2 models can improve the performance of the sequential model by 50.8 and 61.6 percent, respectively.