Browsing by Author "SHUNG, CB"

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A 30-MHZ TRELLIS CODEC CHIP FOR PARTIAL-RESPONSE CHANNELS
(1991-12-01)
SHUNG, CB
;
SIEGEL, PH
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THAPAR, HK
;
KARABED, R
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電子工程學系及電子研究所
We present a rate 8/10 matched-spectral-null (MSN) trellis codec chip which can increase noise tolerance in partial-response channels applicable to digital magnetic recording. The Viterbi detector in this codec features an area-efficient pipelined architecture and a modulo metric normalization technique. The chip was implemented in a 1.2-mu-m CMOS process with a die size of 22 mm2. It offers a 12-Mb/s data rate when operating at 30 MHz. Experimental results verified the predicted coding gain of 2.8 dB relative to the uncoded system at a bit-error rate of 10(-7).
A HIGH SPEED REED-SOLOMON CODEC CHIP USING LOOKFORWARD ARCHITECTURE
(1994)
CHANG, JY
;
SHUNG, CB
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
AN INTEGRATED CAD SYSTEM FOR ALGORITHM-SPECIFIC IC DESIGN
(1991-04-01)
SHUNG, CB
;
JAIN, R
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RIMEY, K
;
WANG, E
;
SRIVASTAVA, MB
LAGER is an integrated computer-aided design (CAD) system for algorithm-specific integrated circuit (IC) design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of new CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout and with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high sample rate applications. A number of algorithm-specific IC's designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip will be described.
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY
(1993-04-01)
SHUNG, CB
;
LIN, HD
;
CYPHER, R
;
SIEGEL, PH
;
THAPAR, HK
The Viterbi algorithm has been widely applied to many decoding and estimation applications in communications and signal processing. A state-parallel implementation is usually used in which one add-compare-select (ACS) unit is devoted to each state in the trellis. In this paper we present a systematic approach of partitioning, scheduling, and mapping the N trellis states to P ACS's, where N > P. The area saving of our architecture comes from the reduced number of both the ACS's and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the area-efficient architecture offers a favorable (smaller) area-time product, compared to a state-parallel implementation. These results will be demonstrated by application examples in the accompanying paper.
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
(1993-05-01)
SHUNG, CB
;
LIN, HD
;
CYPHER, R
;
SIEGEL, PH
;
THAPAR, HK
In the previous paper, we established the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm. In this paper, we will show area-efficient architectures for practical codes to illustrate the design procedures and demonstrate the favorable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes will be presented. We will also discuss the application of our area-efficient techniques to codes with a very large numbers of states, codes with time-varying trellises, and a programmable Viterbi decoder.
FAULT-TOLERANT ARCHITECTURES FOR SHARED BUFFER MEMORY SWITCH
(1994)
LIN, YF
;
SHUNG, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHM
(1993-01-01)
CYPHER, R
;
SHUNG, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The trace-back technique is an effective approach for survivor memory management in the Viterbi algorithm. It is especially attractive when the number of states in the trellis is large, in which case the register exchange approach is impractical due to the area required for wiring. Previous descriptions of the trace-back technique have assumed either one or two trace-back pointers and have made specific assumptions about the speeds of those pointers. In this paper we present a general framework for implementing the trace-back technique with any number of traceback pointers and with relaxed assumptions about the speeds of the pointers. We also show that the use of additional trace-back pointers reduces the memory requirements. Two implementations of the generalized trace-back techniques based on standard RAMs and custom shift registers are presented.
REAL-TIME RECORDING RESULTS FOR A TRELLIS-CODED PARTIAL-RESPONSE (TCPR) SYSTEM
(1993-11-01)
THAPAR, HK
;
SHUNG, CB
;
RAE, JW
;
KARABED, R
;
SIEGEL, PH
This paper describes the results of an experimental performance comparison between a Trellis-Coded Partial Response (TCPR) system and a Partial Response Maximum Likelihood (PRML) channel, using magneto-resistive (MR) recording heads and metal film disks. Measured data confirms that the TCPR method provides substantial performance advantage in terms of ontrack error rate, offtrack capability, and areal density.
SHARED BUFFER ATM SWITCH WITH DOUBLY LINKED LISTS
(1995-07-01)
LIN, YF
;
SHUNG, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The shared buffer memory switch (SBMS) architecture was originally proposed as an effective approach to implement ATM switch fabrics. However, in this paper we find that if an error occurs in the address chain memory of one linked list which stores the address of the next cell in the shared buffer memory, the erroneous situation will spread over all linked lists in the SBMS in a short time. In order to prevent the fault spread phenomenon, we propose two doubly linked list based architectures to combat address chain failure; these are referred to as the Flush and In-Seq schemes. The first scheme flushes the remaining cells in the faulty queue but collect their addresses for later usage. The second scheme outputs the remaining cells in their correct sequence. From our simulation, if the error injection rate is low, the performance of the In-Seq scheme experiences slight degradation compared with the error-free situation.