Browsing by Author "Sachid, Angada B."

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Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
(2016)
Hu, Vita Pi-Ho
;
Lo, Chang-Ting
;
Sachid, Angada B.
;
Su, Pin
;
Hu, Chenming
Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-to-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.
Monolithic 3D CMOS Using Layered Semiconductors
(2016-04-06)
Sachid, Angada B.
;
Tosun, Mahmut
;
Desai, Sujay B.
;
Hsu, Ching-Yi
;
Lien, Der-Hsien
Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications.
TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology
(2015)
Chen, Min-Cheng
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Lu, Ang-Yu
;
Li, Ming-Yang
A 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time. The TMD FinFET channel is deposited by CVD. Hydrogen plasma treatment of TMD is employed to lower the series resistance for the first time. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.