Browsing by Author "Salahuddin, Sayeef"

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A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications
(2016-02)
Fatah, Faiz Aizad
;
Lin, Yueh-Chin
;
Liu, Ren-Xuan
;
Yang, Kai-Chun
;
Lin, Tai-We
A 60-nm-thick E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor (HEMT) was successfully fabricated and evaluated by using Au/Pt/Ti-based non-annealed ohmic technology for high-speed and low-power logic applications. The device exhibited a minimal SS of 69mV/decade, a lower DIBL of 30mV/V, an ION/IOFF ratio above 1.2 x 10(4) at V-DS = 0.5V and a high f(T) of 378GHz and f(max) of 214GHz at V-DS = 1.0V. These results demonstrate that non-annealed ohmic contacts can be used for fabricating E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs with excellent electrical characteristics. The fabricated HEMTs are likely to find use in future high-speed and low-power logic applications. (C) 2016 The Japan Society of Applied Physics.
Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics
(2016-05)
Lin, Cheng-I
;
Khan, Asif Islam
;
Salahuddin, Sayeef
;
Hu, Chenming
;
電子工程學系及電子研究所
We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation (similar to +/- 3%) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (<= 5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized.
Electrical Characteristics of n, p-In0.53Ga0.47As MOSCAPs With In Situ PEALD-AlN Interfacial Passivation Layer
(2014-08-01)
Quang Ho Luc
;
Chang, Edward Yi
;
Hai Dang Trinh
;
Lin, Yueh Chin
;
Hong Quan Nguyen
The effects of plasma enhanced atomic layer deposition (PEALD)-AlN interfacial passivation layer (IPL) on the Al2O3/In0.53Ga0.47As interfaces qualities are studied with different plasma powers. The improvement in electrical properties, including capacitance-voltage (C-V) hysteresis, frequency dispersion, and interface state densities (D-it) are demonstrated on the Al2O3/n, p-In0.53Ga0.47As MOS capacitors. The excellent C-V behaviors are observed on both type of In0.53Ga0.47As-based MOS devices by performing a thin AlN-IPL at the plasma power of 150 W. To explore the interaction between PEALD-AlN layer and In0.53Ga0.47As surface, X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy analyses have also been characterized.
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).
Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft
(2018-01-01)
Li, Kai-Shin
;
Wei, Yun-Jie
;
Chen, Yi-Ju
;
Chiu, Wen-Cheng
;
Chen, Hsiu-Chih
In this work, we use thermal-ALD to prepare ferroelectric HfZrO2 (HZO) thin film with thickness from 3 to 7 nm for the NC-FinFET's gate stack. The subthreshold swing (SS) was as low as 5 mV/dec (SSmin) over 4 orders of I-D. Lower thermal budget process, CO2 far-infrared laser activation and 400 degrees C Ni silicide are employed in the 2-level metal backend integration for maintaining the orthorhombic phase in HZO thin film and minimizing the hysteresis in IV. NC-FinFET inverter has 77% higher voltage gain compared to FinFET-inverter employing HfO2 gate dielectric. NC-FinFET ring oscillator exhibit small speed and power advantages over FinFET oscillator. For the first time, NC-FET cut-off frequency (F-t) frequency is measured, 23.1 GHz or 23% higher than the control FET Ft. NC-FinFET SRAM was observed to exhibit large noise margin.