Browsing by Author "Samanta, Radhamanjari"

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Clock Tree Aware Post-Global Placement Optimization
(2017-01-01)
Su, Hong-Yan
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Chiang, Po-Ting
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Samanta, Radhamanjari
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Li, Yih-Lang
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資訊工程學系
Power consumption is one of the key optimization objectives for modern integrated circuit designs. More than 40% of the total power consumption is contributed by clock trees due to their high frequency of switching and high capacitance. In the traditional physical design flow, placement is done before clock tree synthesis (CTS). CTS constructs a tree to connect the clock source with all the registers. Therefore, optimization of clock trees is limited by the quality of register placement. This paper proposes a post-global placement optimization procedure that integrates a fast three stage CTS method based on modified k-means clustering technique into a global placer. The fast three stage CTS constructs a virtual clock tree to guide global placement to favor CTS. Then a multi-level clock net contractive force according to the virtual clock tree is inserted to optimize register locations for reducing the clock tree wirelength. The experimental results show that the proposed optimization approach can reduce both the clock tree wirelength and clock net switching power at the cost of slight increase in half perimeter wirelength (HPWL).
LESAR: A Dynamic Line-End Spacing Aware Detailed Router
(2018-01-01)
Wei, Ying-Chi
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Samanta, Radhamanjari
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Li, Yih-Lang
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資訊工程學系
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Department of Computer Science
As the VLSI technology scales down, 193nm optical lithography reaches the limit and one-dimensional (1D) unidirectional style lithography technique emerges as one of the most promising solutions for coming advanced technology nodes. The 1D process first generates unidirectional dense metal lines and then use line-end cutting to form the target patterns with cut masks. If cuts are too close, they will lead to conflicts. Line-end spacing rules become dynamic rather than static because of cut mask and also now need to he followed strictly. Line-end spacing check between two line-end pairs in the same mask has also been regarded as compulsory line-end spacing constraints that have not discussed in previous works yet. Complying with these rules during APR has become a new bottleneck. In this work, we propose to make the router aware of the dynamic line-end spacing rules, including end-end spacing and parity spacing constraints. Experimental results of our proposed router demonstrates that it can effectively expel all end-end spacing violations as well as 75% of parity spacing violations in a reasonable runtime increase of 14%.