Browsing by Author "Samukawa, S."

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First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications
(2019-01-01)
Chang, S. -W.
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Sung, P. -J.
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Chu, T-Y.
;
Lu, D. D.
;
Wang, C. -J.
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.
High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications
(2016-01-01)
Lee, Y. -J.
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Hong, T. -C.
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Hsueh, F. -K.
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Sung, P. J.
;
Chen, C. -Y.
Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) ION and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high I-ON/I-OFF ratio and low subthreshold swing (S.S. similar to 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.
High Performance Silicon N-channel Gate-All-Around Junctionless Field Effect Transistors by Strain Technology
(2016)
Sung, P. -J.
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Cho, T. -C.
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Chen, P. -C.
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Hou, F. -J.
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Lai, C. -H
In this paper, strain effects on silicon n-channel gate-allaround (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (I-on/I-off > 10(9)) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.
Tuning of the electron g factor in defect-free GaAs nanodisks
(2015-12-15)
Yang, Li-Wei
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Tsai, Yi-Chia
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Li, Yiming
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Higo, Aiko
;
Murayama, Akihiro
We theoretically study the impact of changes in surroundings on the electron ground-state effective g factor in defect-free GaAs/AlGaAs nanodisks. To perform the study, we formulate and deploy a computational efficient full three-dimensional model to describe the effective g-factor tensor in semiconductor nano-objects of complex geometry and material content. This model is based on an effective 2 x 2 conduction-band Hamiltonian which includes the Rashba and Dresselhaus spin-orbit couplings. The description is suited to clarify the important question of the controllability of the electron effective g factor in semiconductor nano-objects. The results of this theoretical study suggest that in the defect-free GaAs/AlGaAs nanodisks, the effective g factor can be tuned within a wide range by proper design of the nanodisk environment. The zz components of the electron effective g-factor tensor obtained in our simulation are in good agreement with some recent experimental observations.
Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications
(2018-01-01)
Sung, P. -J.
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Chang, C. -Y.
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Chen, L. -Y.
;
Kao, K. -H.
;
Su, C. -J.
For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 degrees C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.