Browsing by Author "Sarkar, Chandan Kumar"

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Comparative Assesment of Ground Plane and Strained based FDSOI MOSFET
(2015-03-01)
Singh, Avtar
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Adak, Sarosij
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Pardeshi, Hemant
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Sarkar, Arghyadeep
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Sarkar, Chandan Kumar
In the present work, we have investigated the performance of ground plane and strained silicon on FDSOI MOSFETs. The 2D ATLAS simulations are done and the simulation model is validated with previously published experimental results. The transfer characteristics, DIBL, Vt, Ion and Ioff of all the structures are analyzed for 25 nm and 32 nm gate length. The effect of body thickness on device performance is also evaluated. Strained device offer higher drive current, but increases the leakage current. We have applied the ground plane to reduce the leakage current. The DIBL is higher for the strained device. DIBL in GPS and GPB structures (strained and unstrained) is almost same, and is lower than conventional FDSOI structure. The FDSOI devices have the lowest threshold voltage as compared to the GP and GPB devices, with GPB offering the highest Vt. The drain current is observed to increases almost linearly with body thickness. The deployment of ground plane and strained silicon on FDSOI MOSFET shows promise to substitute conventional MOSFET for high speed and low power applications.
High performance AlInN/AlN/GaN p-GaN back barrier Gate-Recessed Enhancement-Mode HEMT
(2014-11-01)
Adak, Sarosij
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Sarkar, Arghyadeep
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Swain, Sanjit
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Pardeshi, Hemant
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Pati, Sudhansu Kumar
In the present work, we propose and perform extensive simulation study of the novel device structure having a p-GaN back barrier layer inserted in the conventional AlInN/AlN/GaN Gate-Recessed Enhancement-Mode HEMT device for reducing the short channel effects, gate leakage and enhancing the frequency performance. The influence of the p-GaN back barrier layer on the device performance of the newly proposed structure is done using 2D Sentaurus TCAD simulations. The simulations use Drift Diffusion (DD) model, Masetti and Canali model, which are calibrated/validated with the previously published experimental results. Simulation are done to analyze the transfer characteristics, transconductance (g(m)), Gate leakage current (I-g), drain induced barrier lowering (DIBL), subthreshold slope (SS), threshold voltage (Vth), On-current Off-current ratio (I-on/l(off)), gate capacitance (C-gg) and cut off frequency (f(r)) of the proposed device. A comparison is done between the device without back barrier layer and the proposed device with p-GaN back barrier layer. Use of p-GaN back barrier layer helps to achieve a higher positive Vth due to the depletion effect, reduced I-g, reduced DIBL, prevents degradation of SS and helps to increase the f(T). Very impressive f(r) up to 123 GHz, as compared to 70 GHz for the device without back barrier. These results indicate that AlInN/AlN/GaN Gate-Recessed Enhancement-Mode HEMT structure with p-GaN back barrier is a promising candidate for microwave and switching application. (C) 2014 Elsevier Ltd. All rights reserved.