Browsing by Author "Shann, Jean Jyh-Jiun"

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Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration
(2011-09-01)
Wu, I-Wei
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Chung, Chung-Ping
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Instruction set extension (ISE) is an effective approach to improve the processor performance without tremendous modification in its core architecture. To execute ISE(s), a processor core must be augmented with a new functional unit, called application specific functional unit (ASFU), which consists of multiple hardware implementation options of ISEs (ISE_HW). Obviously, since ISE_HW increases the production cost of a processor core, minimizing the area size of ISE_HW becomes important for ISE exploration. On the other hand, because of different requirements in space and speed, ISE_HW usually has multiple hardware implementation options. Under pipeline-stage timing constrain:, some of these options may have the same performance improvement but entail different hardware costs. According to this phenomenon, the area size of ISE_HW can be reduced by performing hardware design space exploration of ISE_HW. Therefore, in this paper, we propose an ISE exploration algorithm that explores not only ISE but also the hardware design space of ISE_HW. Compared with the previous research, our approach resulted in significant improvement in area efficiency and the execution performance.
Dynamic Memory Optimization and Parallelism Management for OpenCL
(2014-01-01)
Hsu, Chao-Hung
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Wu, I-Wei
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Recently, multiprocessor platforms have become trends for achieving high performance. OpenCL (Open Computing Language) is one of the programming standards for heterogeneous multiprocessors, and provides portability for these platforms. Our research focuses on platforms with CPUs and GPUs since GPUs are now widespread in use. On such a platform, two programming issues may affect the performance on GPU computing significantly. One is the work load distribution and another is the employment of GPU memory hierarchy. To fully utilize the characteristics of GPUs, programmers have to be not only proficient at parallel programming but also familiar with hardware specifications. Therefore, in this paper, we propose a compilation pass to automatically perform optimizations for OpenCL kernels. Our compilation pass will transform an input naive kernel function with optimizations, including kernel function analysis, work- group rearrangement, memory coalescing, and work-item merge. In addition, our framework is implemented on a runtime system so that it may dynamically adjust the optimizing parameters according to the hardware specifications. Considering the execution time, the optimized kernels generated by our design may have significant performance improvement over the naive versions. Although the optimizations performed in runtime may incur time overheads, the overheads may be covered by intensive kernel computation or massive input data in most cases.
Extended Instruction Exploration for Multiple-Issue Architectures
(2014-11-01)
Wu, I-Wei
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Shann, Jean Jyh-Jiun
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Hsu, Wei-Chung
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Chung, Chung-Ping
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交大名義發表
In order to satisfy the growing demand for high-performance computing in modern embedded devices, several architectural and microarchitectural enhancements have been implemented in processor architectures. Extended instruction (EI) is often used for architectural enhancement, while issuing multiple instructions is a common approach for microarchitectural enhancement. The impact of combining both of these approaches in the same design is not well understood. While previous studies have shown that EI can potentially improve performance in some applications on certain multiple-issue architectures, the algorithms used to identify EI for multiple-issue architectures yield only limited performance improvement. This is because not all arithmetic operations are suited for EI for multiple-issue architectures. To explore the full potential of EI for multiple-issue architectures, two important factors need to be considered: (1) the execution performance of an application is dominated by critical (located on the critical path) and highly resource-contentious (i.e., having a high probability of being delayed during execution due to hardware resource limitations) operations, and (2) an operation may become critical and/or highly resource contentious after some operations are added to the EI. This article presents an EI exploration algorithm for multiple-issue architectures that focuses on these two factors. Simulation results show that the proposed algorithm outperforms previously published algorithms.
Improving Performance of JNA by Using LLVM JIT Compiler
(2013)
Tsai, Yu-Hsin
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Wu, I-Wei
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Liu, I-Chun
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Shann, Jean Jyh-Jiun
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資訊工程學系
Java Native Access (JNA) has been proposed to alleviate the burden of programming in Java Native Interface (JNI). JNA allows programmer to call native functions without writing any JNI codes. However, JNA suffers from some performance degradation. To overcome this problem, in this paper, we modify the JNA source code and integrate the LLVM JIT compiler into JNA to improve the performance. Our experiment achieves about 8% to 16% performance improvement for calling a native function with different types and numbers of arguments. Furthermore, our design is a non-traditional way of using the runtime compiler, and the challenges we encountered may help other researchers to face the similar situations.
Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture
(2015-01-01)
Liu, I-Chun
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Wu, I-Wei
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Binary translation is one of the most important techniques of virtualization. The main purpose of a binary translator (BT) is to translate an executable from a source instruction set architecture (ISA) to a target ISA. Traditionally, there are two types of binary translators: static binary translator (SBT) and dynamic binary translator (DBT). In recent years, a new type of BT called hybrid binary translator (HBT) was proposed, which translates the source executable first at static time, and then, at run time, if the execution of the target executable emits an exception because of reaching statically untranslated code, it switches to the attached dynamic translator for translating these code. Therefore, an HBT may have the merits of both good performance of SBT and easy handling of code discovery and code location problems of DBT. Nowadays, massive application programs have been developed for x86 platforms, and thus, many binary translators have been proposed for x86 ISA. However, due to the characteristics of CISC architecture of x86, for example, variable-length instruction format, the BT designed for it previously usually apply dynamic translation strategy or make use of profiling data for resolving the code discovery and code location problems. In this paper, we present an HBT which supports x86 ISA and emulates the execution behavior of an x86 executable under Linux operation system. In our x86-32 to x86-64 translation experiments, the target executables translated by our HBT outperform that of QEMU on most programs of EEMBC benchmark suite.
Modification and implementation of an edge-based fast intra prediction mode decision algorithm for H.264/AVC high resolution real-time systems
(2012-02-01)
Chiang, Kuen-Cheng
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Wu, Ming Feng
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
In this paper, we propose an architecture for H.264/AVC fast intra-prediction-mode decision making in high resolution real-time applications. Intra-prediction-mode decision making requires many computations of H.264/AVC video coding, and also extra time for mode generation for intra prediction mode decisions. Hence, there exists a bottleneck in the execution of high resolution real-time applications. To improve the operation of intra prediction mode decision, we use an algorithm which, based on the edge information of an object, will reduce estimations of mode predictions by 66%; with negligible loss of video quality and a small increase in bit-rate of video stream. We propose a low cost architecture, with gate counts reduced by 50% compared with former design. The total gate count is 86,671 and the maximum operating frequency is 250 MHz using TSMC 0.18 mu m cell-based technology. The experimental results show our design is a strong competitor with most modern high resolution, real-time video processing. (C) 2011 Elsevier Inc. All rights reserved.
Prefetching for Array Data in Embedded Java Hardware Accelerator
(2009)
Wu, Yi-Ruei
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Chen, Yu-Sheng
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
For improving the efficiency of a program, it is important to reduce stalls caused by memory access. Traditional programs usually spend much time on memory stalls when accessing lower-level memory, and so do Java programs. In order to reduce memory stall time, prefetching is a feasible solution. We observed some obvious properties of array access so that we could prefetch array data by taking advantage of these properties. We analyzed these properties and proposed a suitable array prefetching mechanism for embedded Java hardware accelerators so as to reduce the time spent on memory stalls, Our approach eliminates about 25% of array stall time on average and even up to 50% for some array-based programs.
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors
(2015-07-01)
Wu, I-Wei
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Shann, Jean Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
Next-generation digital entertainment and mobile communication devices are anticipated to require greater processor performance. To meet these demands, several researchers have attached a reconfigurable hardware accelerator to the base processor core. The reconfigurable hardware accelerator, termed a reconfigurable customized functional unit (RCFU), is usually realized by multiple processing elements (PE) organized in matrix form. The structure of the RCFU is generated from hot operation patterns of specific applications. Other than the RCFU, \'multiple-issue\' is another microarchitectural technique to increase the performance. However, the impact of combining both of these approaches in the same design is not yet well understood. This problem motivates us to design RCFU generation and exploitation algorithms for a multiple-issue processor. To allow more operations to execute on the RCFU simultaneously, the proposed generation algorithm merges several data-independent operation patterns to construct the RCFU architecture. To schedule operations on both the RCFU and functional units (FU) of the base processor core simultaneously, the proposed exploitation algorithm presents a model to represent all available computing resources from both the FUs of the base processor and the PEs in the RCFU. Using this model, the RCFU exploitation problem can be considered as an instruction-scheduling problem. Our experiment achieves an average improvement in execution performance of 50% compared with previous efforts [2, 5].
Run-time reconfiguration scheduling of 3D-rendering on a reconfigurable system
(2005)
Chiang, Kuen-Cheng
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Lee, Meng-Tho
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Shann, Jean Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
With the dramatically increasing demands for multimedia processing capabilities in portable electronic devices, the architectural supports for various multimedia computations in one platform are crucial to the success of a product. Although application-specific accelerators have performance advantages, their inflexibilities seriously impede the applicability and shorten product lifetime. On the other hand, a general-purpose processor has benefits to wide applicability but can not meet the real-time criteria in many cases. Therefore, we develop a platform consisting of a general-purpose CPU, an array of processing elements, and a shared memory to transfer data between them. In addition, we propose two scheduling methods, First-Come-First-Serve and Priority, to process the 3D models with a better performance. Experimental results indicate that the priority scheduling significantly improves the 3D-rendering in both computation speed and silicon area, compared with FCFS scheduling. Given the same speed requirements on both FCFS and priority scheduling methods, the priority scheduling requires only 75% of the silicon area. On the other hand, it yields 30% to 80% speedup with the same area. Moreover, with priority scheduling, its performance advantage can be further increased by skills such as partial reconfiguration and multi-context configuration, to reduce its reconfiguration overhead.
Translating OpenACC Program for HAS Environment
(2017-01-01)
Lo, Han-Ping
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Heterogeneous System Architecture (HSA) is a newly arising heterogeneous multiprocessor platform which may improve the heavy data transmission between CPU and GPU in traditional heterogeneous multiprocessor platforms through shared virtual memory. However, as other heterogeneous multiprocessor platforms, it is complex and error -prone to write HSA programs. Therefore, we design and implement a translation framework based on LLVM for automatically translating OpenACC programs, directive -based parallel programming programs, into HSA programs. The main components of the framework include an extension version of Clang, a PLIR-annotation parser, and an HAS host/kernel IR generator. The experiment result shows that the translated HSA programs generated by our OpenACC compiler achieve 7.78x speedups in average with respect to the corresponding sequential programs. Moreover, compared with the OpenMP compiler proposed by HSA foundation, our OpenACC compiler achieves 2.91x speedups in average.
Translating OpenACC to LLVM IR with SPIR Kernels
(2016)
Peng, Hao-Wei
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
In general, highly parallelized programs executed on heterogeneous multiprocessor platforms may get better performance than homogeneous ones. OpenCL is one of the standards for parallel programming of heterogeneous multiprocessor platforms and SPIR (Standard Portable Intermediate Representation) is a portable binary format for representing OpenCL kernel code. However, the programming of these programs is usually complex and error-prone for most programmers. Therefore, some standards have been proposed to simplify the programming on heterogeneous multiprocessor platforms, for example, OpenACC (a directive-based parallel programming model). In this paper, we implement our framework on Clang, the C front-end of LLVM, to automatically translate OpenACC to LLVM IR with SPIR kernels. After that, it is optional to optimize the IR code by LLVM optimizer and execute the host LLVM IR by LLVM JIT-compiler. According to the experiment results, our translated programs have significant performance enhancement for some programs while comparing with their corresponding sequential version of programs and have comparable performance while comparing with their manual OpenCL version. Therefore, our design may reduce the difficulty of writing the programs in heterogeneous multiprocessor platform and the translated OpenCL programs are portable and have good performance as that of the manual OpenCL programs written by experienced programmers.