Browsing by Author "Shaw, Jonathan"

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Integration of Self-Assembled Redox Molecules in Flash Memory Devices
(2011-03-01)
Shaw, Jonathan
;
Zhong, Yu-Wu
;
Hughes, Kevin J.
;
Hou, Tuo-Hung
;
Raza, Hassan
Self-assembled monolayers (SAMs) of either ferrocenecarboxylic acid or 5-(4-Carboxyphenyl)-10,15,20-triphenylporphyrin-Co(II) (CoP) with a high-kappa dielectric were integrated into the Flash memory gate stack. The molecular reduction-oxidation (redox) states are used as charge storage nodes to reduce charging energy and memory window variations. Through the program/erase operations over tunneling barriers, the device structure also provides a unique capability to measure the redox energy without strong orbital hybridization of metal electrodes in direct contact. Asymmetric charge injection behavior was observed, which can be attributed to the Fermi-level pinning between the molecules and the high-kappa dielectric. With increasing redox molecule density in the SAM, the memory window exhibits a saturation trend. Three programmable molecular orbital states, i.e., CoP(0), CoP(1-), and CoP(2-), can be experimentally observed through a charge-based nonvolatile memory structure at room temperature. The electrostatics is determined by the alignment between the highest occupied or the lowest unoccupied molecular orbital (HOMO or LUMO, respectively) energy levels and the charge neutrality level of the surrounding dielectric. Engineering the HOMO-LUMO gap with different redox molecules can potentially realize a multibit memory cell with less variation.
Statistical Metrology of Metal Nanocrystal Memories With 3-D Finite-Element Analysis
(2009-08-01)
Shaw, Jonathan
;
Hou, Tuo-Hung
;
Raza, Hassan
;
Kan, Edwin Chihchuan
;
電子工程學系及電子研究所
We study the parametrical yield of memory windows for the metal nanocrystal (NC) Flash memories with consideration of the 3-D electrostatics and channel percolation effects. Monte Carlo parametrical variation that accounts for the number and size fluctuations in NCs as well as channel length is used to determine the threshold voltage distribution and bit error rate for gate length scaling to 20 nm. Devices with nanowire-based channels are compared with planar devices having the same gate stack structure. Scalability prediction by 1-D analysis is found to be very different from 3-D modeling due to underestimation of effective NC coverage and failure to consider the 3-D nature of the channel percolation effect.