Browsing by Author "Shen, Chang-Hong"

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3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
(2012-01-01)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Hsieh, Wei-Shang
;
Tu, Cheng-Hui
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
A sandwiched buffer layer enabling pulsed ultraviolet- and visible-laser annealings for direct fabricating poly-Si field-effect transistors on the polyimide
(2017-07-10)
Kao, Ming-Hsuan
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Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
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Lee, Pei-Kang
A sandwiched buffer layer of SiO2/Al/SiO2 enables ultraviolet-laser crystallization and visible-laser activation for direct fabrication of a poly-Si flexible field-effect-transistor (fFET) on polyimides. The buffer layer can produce heat accumulation and laser reflection from the Al/SiO2 interface to facilitate grain growth and contact resistance reduction of poly-Si without damaging the polyimide substrate. The feature size of poly-Si fFET has shrunk to 400nm via laser annealing, with the on/off current-ratio exceeding 5 x 10(6) and a subthreshold swing of 190 mV/dec. Moreover, the transfer characteristics of fFET by tension stress can be maintained until the bending radius reaches over 15 mm. Published by AIP Publishing.
a-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
(2016)
Kao, Ming-Hsuan
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Yang, Chih-Chao
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Wu, Tsung-Ta
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Hsieh, Tung-Ying
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Huang, Wen-Hsieh
Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low I-off and high I-on operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm(2)) under 450 lux indoor illumination, envisions self-power and low cost 3D(+)IC for internet of things.
AlN Surface Passivation of GaN-Based High Electron Mobility Transistors by Plasma-Enhanced Atomic Layer Deposition
(2017-04-27)
Tzou, An-Jye
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Chu, Kuo-Hsiung
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Lin, I-Feng
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Ostreng, Erik
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Fang, Yung-Sheng
We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 degrees C. The AlN was grown by N-2-based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H-2/NH3 plasma pretreatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias (V-DSQ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage (V-th), corresponding to a 40.2% of current collapse at 150 degrees C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.
Approaching conversion limit with all-dielectric solar cell reflectors
(2015-02-09)
Fu, Sze Ming
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Lai, Yi-Chun
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Tseng, Chi Wei
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Yan, Sheng Lun
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Zhong, Yan Kai
Metallic back reflectors has been used for thin-film and wafer-based solar cells for very long time. Nonetheless, the metallic mirrors might not be the best choices for photovoltaics. In this work, we show that solar cells with all-dielectric reflectors can surpass the best-configured metal-backed devices. Theoretical and experimental results all show that superior large-angle light scattering capability can be achieved by the diffuse medium reflectors, and the solar cell J-V enhancement is higher for solar cells using all-dielectric reflectors. Specifically, the measured diffused scattering efficiency (D.S.E.) of a diffuse medium reflector is >0.8 for the light trapping spectral range (600nm-1000nm), and the measured reflectance of a diffuse medium can be as high as silver if the geometry of embedded titanium oxide(TiO2) nanoparticles is optimized. Moreover, the diffuse medium reflectors have the additional advantage of room-temperature processing, low cost, and very high throughput. We believe that using all-dielectric solar cell reflectors is a way to approach the thermodynamic conversion limit by completely excluding metallic dissipation. (C) 2015 Optical Society of America
Charge-trap non-volatile memories fabricated by laser-enabled low-thermal budget processes
(2015-11-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Pan, Fu-Ming
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Yang, Chih-Chao
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Shen, Chang-Hong
We fabricated charge-trap non-volatile memories (NVMs) using low thermal budget processes, including laser-crystallization of poly-Si thin film, chemical vapor deposition deposition of a stacked memory layer, and far-infrared-laser dopant activation. The thin poly-Si channel has a low defect-density at the interface with the bulk, resulting in a steep subthreshold swing for the NVM transistors. The introduction of the stacked SiO2/AlOxNy tunnel layer and the SiNx charge-trap layer with a gradient bandgap leads to reliable retention and endurance at low voltage for the NVMs. The low thermal budget processes are desirable for the integration of the nano-scaled NVMs into system on panels. (C) 2015 AIP Publishing LLC.
CIGS solar cell integrated with high mobility microcrystalline Si TFTs on 30X40 cm(2) glass panels for self powered electronics
(2012-01-01)
Shen, Chang-Hong
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Shieh, Jia-Min
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Wu, Tsung-Ta
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Huang, Jung Y.
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Huang, Che-Hsuan
For the first time, we report a novel self-powered TFT panel (30X40cm(2)) by integration of sputtering/non-toxic Se vapor selenization copper-indium-gallium-selenide (CIGS) solar cell (conversion efficiency of 8%) and high electron-mobility (172 cm(2)/V-s) micro-crystalline (mu c)-Si TFTs.
CO2 laser annealing of low-hole-concentration polycrystalline germanium for the fabrication of enhancement-mode nMOSFET
(2018-10-01)
Kasirajan, Han Anand
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Huang, Wen-Hsien
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Kao, Ming-Hsuan
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Wang, Hsing-Hsiang
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Shieh, Jia-Min
A p-type polycrystalline Ge (poly-Ge) film processed by UV and CO2 laser annealing reduces the hole concentration from 6 x 10(18) to 2 x 10(16) cm(-3), accompanied by poly-grain growth. The decrease in hole concentration arises from the defect annealing using a CO2 laser, as demonstrated by the changes in the work function, that is, the valence-band maximum (VBM). The laser processes reduce the thermal budget for the fabrication of an enhancement-mode poly-Ge nMOSFET, which has a l(on)/l(off) ratio of 5 x 10(3), a Vth of 2V, and a subthreshold swing of 250 mV/dec., and will be potential fabrication methods for monolithic 3D integrated circuits in the future. (C) 2018 The Japan Society of Applied Physics
DC and high-frequency characteristics of trigate polycrystalline-silicon thin-film transistors with different layout geometries
(2019-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Shiao, Yu-Shao Jerry
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Lin, Chuang-Ju
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Huang, Guo-Wei
In this paper, we present the dc and high-frequency characteristics of trigate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) for RF applications. Trigate TFTs were fabricated using a 3D-IC process and designed with a multi-finger gate and multi-channel configuration. To obtain an optimal device design guideline, different source/drain (S/D) extension dimensions and channel layouts are investigated. We find that devices with a shorter or wider extension have higher cutoff frequencies (f(T)) and maximum oscillation frequencies (f(max)) owing to their lower S/D resistances. In addition, the high-frequency performance can be further improved by adopting the tapered channel structure, where the channel width increases gradually from the source to the drain. For the optimal device designs, the values of f(T) and f(max) are around 25 GHz and 30 GHz, respectively. The high f(T) and f(m)(ax) as well as excellent gate controllability in our devices indicate the trigate poly-Si TFT could be a suitable candidate for low-cost RFIC applications. (C) 2019 The Japan Society of Applied Physics
Down Shifted Converssion for Enhanceed HIT SSolar Cell Efficiency
(2017-01-01)
Lin, Albert S.
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Parashar, Parag
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Huang, Wei-Ming
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Huang, Yi-Wen
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Jian, Ding-Rung
In this work, HIT solar cell is incorporated with the luminescent down-shifting (LDS) mechanism for the incident solar spectrum. The heterojunction with intrinsic thin-layer(HIT) solar cell is highly efficient, low temperature (200 C), low cost, and highly symmetrical device. Nevertheless, the carrier collection efficiency is low for the short wavelength solar photons due to the surface recombination. Here, a thin phosphor layer is spray coated on the top of HIT solar cells for the luminescent down-shifting of high energy photons and thus enhanced external quantum efficiency (EQE) for the device for lambda=300nm-450nm is observed.
Embedded biomimetic nanostructures for enhanced optical absorption in thin-film solar cells
(2011-07-04)
Tsai, Min-An
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Han, Hao-Wei
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Tsai, Yu-Lin
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Tseng, Ping-Chen
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Yu, Peichen
Light-management is critical to thin film solar cells due to their usually limited optical absorption in the active layer. Conventional approaches involve employing separate techniques for anti-reflection and light trapping. Here, we demonstrate an embedded biomimetic nanostructure (EBN) that achieves both effects for hydrogenated amorphous silicon (a-Si: H) solar cells. The fabrication of EBNs is accomplished by patterning an index-matching silicon-nitride layer deposited on a glass substrate using polystyrene nanospheres lithography, followed by reactive ion etching. The profile of EBN is then reproduced layer by layer during the deposition of a-Si: H cells. We show that a solar cell with an optimized EBN exhibits a broadband enhanced external quantum efficiency due to both antireflection and light-trapping, with respect to an industrial standard cell using an Asahi U glass substrate which is mostly optimized for light trapping. Overall, the cell with an optimized EBN achieves a large short-circuit current density of 17.74 mA/cm(2), corresponding to a 37.63% enhancement over a flat control cell. The power conversion efficiency is also increased from 5.36% to 8.32%. Moreover, the light management enabled by the EBN remains efficient over a wide range of incident angles up to 60 degrees, which is particularly desirable for real environments with diffused sun light. The novel patterning method is not restricted to a-Si:H solar cells, but is also widely applicable to other thin film materials. (C) 2011 Optical Society of America
Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing
(2017-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Kao, Ming-Hsuan
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Shen, Chang-Hong
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Huang, Tzu-En
A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 x 10(19) cm(-3) and a narrow Raman FWHM of 3.9 cm(-1). Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I-on/I-off ratio of 6 x 10(4), V-th of % -0.3 V, and a subthreshold swing of 237mV/dec at V-d of 1V and DIBL of 101mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V-th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics. (C) 2017 The Japan Society of Applied Physics
Environmentally and Mechanically Stable Selenium 1D/2D Hybrid Structures for Broad-Range Photoresponse from Ultraviolet to Infrared Wavelengths
(2018-10-17)
Chen, Yu-Ze
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You, Yen-Ting
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Chen, Pin Jung
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Li, Dapan
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Su, Teng-Yu
Selenium (Se) is one of the potential candidates as photodetector because of its outstanding properties such as high photoconductivity (similar to 8 x 10(4) S cm(-1)), piezoelectricity, thermoelectricity, and nonlinear optical responses. Solution phase synthesis becomes an efficient way to produce Se, but a contamination issue that could deteriorate the electric characteristic of Se should be taken into account. In this work, a facile, controllable approach of synthesizing Se nanowires (NWs)/films via a plasma-assisted growth process was demonstrated at the low substrate temperature of 100 degrees C. The detailed formation mechanisms of nanowires arrays to thin films at different plasma powers were investigated. Moreover, indium (In) layer was used to enhance the adhesive strength with 50% improvement on a SiO2/Si substrate by mechanical interlocking and surface alloying between Se and In layers, indicating great tolerance for mechanical stress for future wearable devices applications. Furthermore, the direct growth of Se NWs/films on a poly(ethylene terephthalate) substrate was demonstrated, exhibiting a visible to broad infrared detection ranges from 405 to 1555 nm with a high on/off ratio of similar to 700 as well as the fast response time less than 25 ms. In addition, the devices exhibited fascinating stability in the atmosphere over one month.
Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing
(2012-04-02)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Tu, Cheng-Hui
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Wang, Chieh
The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 mu s under low operating voltages of +/-7V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3700729]
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
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Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester
(2014)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Chen, Chien-Fu
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (< 15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm(2) layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.
High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
(2017-05-02)
Wu, Tsung-Ta
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Huang, Wen-Hsien
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Yang, Chih-Chao
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Chen, Hung-Chun
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Hsieh, Tung-Ying
Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (I-on)/subthreshold swing (S.S.) of 181 mu A/mu m/107 mV/dec and 188 mu A/mu m/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at V-DD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
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Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
High-performance p-channel thin-film transistors with lightly doped n-type excimer-laser-crystallized germanium films
(2017-06-01)
Liao, Chan-Yu
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Huang, Ching-Yu
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Huang, Ming-Hui
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Huang, Wen-Hsien
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Shen, Chang-Hong
High-performance polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) fabricated with lightly doped Ge thin films by excimer laser crystallization (ELC) and counter doping (CD) have been demonstrated. High-quality n-type Ge thin films with a grain size as large as 1 mu m were fabricated by ELC in the super lateral-growth regime and CD at a dose of 1 x 10(13) cm(-2) or higher. Consequently, a superior field-effect mobility of 271cm(2)V(-1)s(-1) and a high on/off current ratio of 2.7 x 10(3) have been obtained for p-channel Ge TFTs with the channel width and length of both 0.5 mu m fabricated by ELC at 300mJ/cm(2) and CD at a dose of 1 x 10(13)cm(-2). The effects of ELC conditions and CD dose on the electrical characteristics of p-channel Ge TFTs were also investigated. (C) 2017 The Japan Society of Applied Physics.
High-Performance Recessed-Channel Germanium Thin-Film Transistors via Excimer Laser Crystallization
(2018-03-01)
Liao, Chan-Yu
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Chen, Shih-Hung
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Huang, Wen-Hsien
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Shen, Chang-Hong
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Shieh, Jia-Min
This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grainswith a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from unmelted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect holemobility of 447 cm(2)V(-1)s(-1) with minor performance deviation.