Browsing by Author "Shen, WZ"

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A new method for constructing IP level power model based on power sensitivity
(2000-12-01)
Huang, HL
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Lin, JY
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Shen, WZ
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Jou, JY
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電子工程學系及電子研究所
As the function uf a system getting more complex. IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of tilt ir IP blocks a secret. An IP level power model is a model that takes only the primary) input statistics its parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method, fur power models based oil power sensitivities. BS analyzing the relationship between the dynamic power consumption uf CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis. the first nominal point is selected to minimize the average Estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can he applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby. it is a promising method for IP level power model construction.
A power modeling and characterization method for macrocells using structure information
(1997)
Lin, JY
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Shen, WZ
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Jou, JY
;
交大名義發表
;
電子工程學系及電子研究所
To characterize a macrocell, a general method is to stare the power consumption of all possible transition events at primary inputs in the lookup tables, Though this approach is very accurate, the lookup tables could be huge for tile macrocells with many inputs, In this paper, we present a new power modeling method which rakes advantage of the structure information of macrocells and selects minimum number of primary inputs or internal nodes in a macrocell as state variables to build a state transition graph (STG). Those state variables can completely model the transitions of ail internal nodes and the primary outputs. By carefully deleting some state variables, we further introduce an incomplete power modeling technique which can simplify the STG without losing much accuracy. In addition, we exploit the properly of the compatible patterns of a macrocell to further reduce the number of edges in the corresponding STG. Experimental results show that our modeling techniques can provide SPICE-like accuracy and can reduce the size of the lookup table significantly comparing to the general approach.
A power modeling and characterization method for the CMOS standard cell library
(1996)
Lin, JY
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Shen, WZ
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Jou, JY
;
交大名義發表
;
電子工程學系及電子研究所
In this paper, we propose power consumption models for complex gates and transmission gates, which are extended from the model of basic gates proposed in [1]. We also describe an accurate power characterization method for CMOS standard cell libraries which accounts for the effects of input slew rare, output loading, and logic state dependencies. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power, and dynamic power. For each component, power equation is derived from SPICE simulation results where the netlist is extracted from cell's layout. Experimental results on a set of ISCAS'85 benchmark circuits show that the power estimation based on our power modeling and characterization provides within 7% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.
A structure-oriented power modeling technique for macrocells
(1999-09-01)
Lin, JY
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Shen, WZ
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Jou, JY
;
電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To characterize the power consumption of a macrocell, a general method involves recording the power consumption of all possible input transition events in the look-up tables. However, though this approach is accurate, the size of the table becomes very large. In this paper, we propose a new power modeling technique that takes advantage of the structural information of a macrocell, In this approach, a subset of primary inputs and internal nodes in the macrocell are selected as the state variables to build a state transition graph (STG), These state variables can model the steady-state transitions completely. Moreover, by selecting the characterization patterns properly, the STG can also model the glitch power in the macrocell accurately. To further simplify the complexity of the STG, an incomplete power modeling technique is presented. Without losing much accuracy, the property of compatible patterns is exploited for a macrocell to further reduce the number of edges in the corresponding STG, Experimental results show that our modeling techniques can provide SPICE-like accuracy, while the size of the look-up table is significantly reduced.
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
(2000-08-01)
Huang, JD
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Jou, JY
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Shen, WZ
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based held programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
(1996)
Huang, JD
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Jou, JY
;
Shen, WZ
;
交大名義發表
;
電子工程學系及電子研究所
In this paper, we propose an iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. First, it finds an area-optimized performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions, the area-optimized one and the performance-optimized one, produced by our algorithm outperform the results of most existing algorithms. Therefore, our algorithm is very useful for the timing driven FPGA synthesis.
CB-Power: A hierarchical cell-based power characterization and estimation environment for static CMOS circuits
(1996)
Shen, WZ
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Lin, JY
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Lu, JM
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交大名義發表
;
電子工程學系及電子研究所
In this paper, we present CB-Power, a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. The environment is based on a cell characterization system for timing, power and input capacitance and on a cell-based power estimator, The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account, The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power, and dynamic power. With the characterization data, a estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of a circuit. CB-Power is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that CB-Power provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.
CB-power: A hierarchical power analysis and characterization environment of cell-based CMOS circuits
(1997-10-01)
Shen, WZ
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Lin, JY
;
Lu, JM
;
交大名義發表
;
電子工程學系及電子研究所
In this paper, we present CB-Porver, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power. short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.
Combinative motion estimation algorithm and the corresponding architecture for complex motion phenomenon
(1998-02-01)
Liu, PC
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Chang, WT
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Shen, WZ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Combining the features of block matching algorithm and block recursive algorithm a new motion estimation method is proposed for complex motion phenomenon. With the full searching procedure used in block matching algorithm and the adaptive searching procedure used in block recursive algorithm, the proposed combinative algorithm can be used to estimate more complex motion parameters such as translation, zoom, rotation and image deformation and get good performance. To reduce the computational complexity, the corresponding architecture of the combinative algorithm is also proposed. With this architecture the computation amount can be largely reduced to make the proposed algorithm can be used for real time motion estimation.
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
(1995)
Huang, JD
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Joy, JY
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Shen, WZ
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Design and performance evaluation of a distributed knockout switch with input and output buffers
(1996-06-01)
Cheng, YJ
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Lee, TH
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Shen, WZ
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電子工程學系及電子研究所
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電信工程研究所
A nonblocking ATM switch with input and output buffers is proposed and its performance is evaluated. The proposed switch is a modified version of an existing distributed-knockout-switch. In the proposed switch architecture, an input port with a nonempty queue always sends a cell to the switch at the beginning of each time slot. The cell sent out from an input port reaches either its destination output port (if it wins the contention) or a different input port (if it loses). A priority scheme is adopted to preserve service-cell sequencing. A cell is discarded if it loses a predetermined number of consecutive contentions. A modified architecture which can provide multicast service is also presented. Simulations are performed to evaluate the proposed switch architecture under both uniform- and hot-spot nonuniform-traffic models.
Design and performance evaluation of a distributed knockout switch with input and output buffers
(1996-06-01)
Cheng, YJ
;
Lee, TH
;
Shen, WZ
;
電子工程學系及電子研究所
;
電信工程研究所
A nonblocking ATM switch with input and output buffers is proposed and its performance is evaluated. The proposed switch is a modified version of an existing distributed-knockout-switch. In the proposed switch architecture, an input port with a nonempty queue always sends a cell to the switch at the beginning of each time slot. The cell sent out from an input port reaches either its destination output port (if it wins the contention) or a different input port (if it loses). A priority scheme is adopted to preserve service-cell sequencing. A cell is discarded if it loses a predetermined number of consecutive contentions. A modified architecture which can provide multicast service is also presented. Simulations are performed to evaluate the proposed switch architecture under both uniform- and hot-spot nonuniform-traffic models.
Fault diagnosis of a distributed knockout switch
(1998-08-01)
Cheng, YJ
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Lee, TH
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Shen, WZ
;
電子工程學系及電子研究所
;
電信工程研究所
The distributed knockout switch has multiple paths between any input and output pair and thus is inherently robust to faults without the need of adding any additional switch elements. However, to achieve fault tolerance, one has to first detect and locate the faults. The authors present an efficient fault diagnosis procedure to detect, locate. and identify the fault type of single switch element faults for the switch element array of the distributed knockout switch. To facilitate fault diagnosis, the operation of switch elements is slightly modified. The diagnosis procedure can locate most single switch element faults in two phases. Faults which cannot be located in two phases can always be located in a third phase. Binary search algorithms are developed to locate some kinds of single switch element faults in the third phase.
Inductance modeling for on-chip interconnects
(2002)
Tu, SW
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Shen, WZ
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Chang, YW
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Chen, TC
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電子工程學系及電子研究所
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable. to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [11] is within 10% for practical cases.
Inductance modeling for on-chip interconnects
(2003-04-01)
Tu, SW
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Shen, WZ
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Chang, YW
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Chen, TC
;
Jou, JY
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout ( placement and routing) tool for inductance ( delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.
Motion parameter estimation based on the block recursive algorithm with finite word length
(1997-11-01)
Liu, PC
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Chang, WT
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Shen, WZ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Three parameter motion model can better describe the motion trajectory of picture element in video sequence. Combining the features of block process and recursive estimation, a block recursive algorithm is proposed to calculate these three motion parameters with compensating the variety of block position to get better stability. To get the simplification requirement for hardware implementation, the representation accuracy of displaced frame difference and gradient that are given is analyzed, From these analysis we propose a quantized block recursive algorithm with quantized grandient to reduce the computational complexity. With this simplification the quantized motion estimation algorithm could get sufficient computational speed to meet the requirement of real time application with the least accuracy loss.
Motion parameter estimation based on the block recursive algorithm with finite word length
(1997-11-01)
Liu, PC
;
Chang, WT
;
Shen, WZ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Three parameter motion model can better describe the motion trajectory of picture element in video sequence. Combining the features of block process and recursive estimation, a block recursive algorithm is proposed to calculate these three motion parameters with compensating the variety of block position to get better stability. To get the simplification requirement for hardware implementation, the representation accuracy of displaced frame difference and gradient that are given is analyzed, From these analysis we propose a quantized block recursive algorithm with quantized grandient to reduce the computational complexity. With this simplification the quantized motion estimation algorithm could get sufficient computational speed to meet the requirement of real time application with the least accuracy loss.
On circuit clustering for area/delay tradeoff under capacity and pin constraints
(1998-12-01)
Huang, JD
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Jou, JY
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Shen, WZ
;
Chuang, HH
;
電子工程學系及電子研究所
In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depth-first-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performance. We then show that this algorithm can be easily extended to solve the clustering problem subject to both capacity and pin constraints. Experimental results show that our algorithm can provide a complete set of clustering solutions from the area-optimized one to the delay-optimized one for a given circuit. Furthermore, comparing to the existing delay-optimized algorithms, ours achieves almost the same performance but with much less area overhead. Therefore, this algorithm is very useful on solving the timing-driven circuit clustering problem.
Recursive minimum energy algorithm for image interpolation
(1998-02-01)
Liu, PC
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Chang, WT
;
Shen, WZ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An interpolation method based on the criterion to maximize the smoothness is proposed. In contrast to the conventional approach, where the interpolated signal is made smooth by low-pass filtering, in the proposed method, the smoothness is obtained by minimizing a global energy function. With the minimum energy formulation for interpolation, a recursive method is used to derive the solution and named as the recursive minimum energy algorithm. Because the smoothness is improved by increasing the calculation iteration but not by increasing the tap length, the controllability of this system is increased. Experiments show that the smoothness and the frequency performance obtained by the proposed algorithm are better than those of the conventional method. Also, the corresponding architecture design for the image interpolation is presented and shown to be suit for VLSI implemented.
Recursive minimum energy algorithm for image interpolation
(1998-02-01)
Liu, PC
;
Chang, WT
;
Shen, WZ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An interpolation method based on the criterion to maximize the smoothness is proposed. In contrast to the conventional approach, where the interpolated signal is made smooth by low-pass filtering, in the proposed method, the smoothness is obtained by minimizing a global energy function. With the minimum energy formulation for interpolation, a recursive method is used to derive the solution and named as the recursive minimum energy algorithm. Because the smoothness is improved by increasing the calculation iteration but not by increasing the tap length, the controllability of this system is increased. Experiments show that the smoothness and the frequency performance obtained by the proposed algorithm are better than those of the conventional method. Also, the corresponding architecture design for the image interpolation is presented and shown to be suit for VLSI implemented.