Browsing by Author "Shen, Wen-Wei"

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2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
(2014-01-01)
Huang, Po-Tsang
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Chou, Lei-Chun
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Huang, Teng-Chieh
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Wu, Shang-Lin
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Wang, Tang-Shuan
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
(2014-12-01)
Huang, Po-Tsang
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Wu, Shang-Lin
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Huang, Yu-Chieh
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Chou, Lei-Chun
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Huang, Teng-Chieh
Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with mu-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of mu-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 x 24 mu-probe array with embedded TSVs is fabricated on a 5 x 5 mm2 chip and bonded on the back side of the interposer. Thus, each channel contains 6 x 6 mu-probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus (mu-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 mu W for 16-channel neural sensing.
3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
(2018-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chen, Shang-Chun
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Chang, Hsiang-Hung
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Chang, Tao-Chih
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications
(2018-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Shen, Wen-Wei
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Huang, Shin-Yi
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Kuo, Tzu-Ying
Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.
Optimization of laser release process for throughput enhancement of fan-out wafer-level packaging
(2018-01-01)
Lee, Chia-Hsin
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Su, Jay
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Liu, Xiao
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Wu, Qi
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Lin, Jim-Wein
Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 mu m thick) with coefficient of thermal expansion of 8 ppm/degrees C were treated by selected laser release layers. After deposition of 0.05-mu m Ti/0.15 mu m Cu on the glass carrier, passivation of around 8 mu m was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-mu m reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.
Process Development and Material Characteristics of TSV-less Interconnection Technology for FOWLP
(2017-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chang, Hsiang-Hung
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Kuo, Tzu-Ying
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Fu, Huan-Chun
Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.
Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)
(2017-01-19)
Shen, Wen-Wei
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.
Ultrathin Glass Wafer Lamination and Laser Debonding to Enable Glass Interposer Fabrication
(2015)
Shen, Wen-Wei
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Chang, Hsiang-Hung
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Wang, Jen-Chun
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Ko, Cheng-Ta
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Tsai, Leon
Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 mu m) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper. Thin glass wafers have reduced mechanical stiffness. Therefore, handling and shipping thin glass wafers (<= 100 mu m) throughout the semiconductor fabrication and packaging assembly processes are critical. Temporary wafer bonding technology is used in this study to bond a thin glass wafer to a carrier to improve the rigidity. Vacuum lamination technology is used in this study as a bonding process to enhance the cost-effectiveness. After processing, the carrier is removed by laser debonding. The thin glass wafer with structures on both sides does not need to undergo a glass thinning process and saves a lot of cost compared to the traditional glass or Si interposer processes. Thin 300-mm glass wafers 100 mu m thick are evaluated as: (a) blank thin glass wafers and (b) thin glass wafers with through-glass vias (TGVs) 30 mu m in diameter. A UV laser with a wavelength of 308 nm, which has the benefit of less impact to the device, was adopted to laser debonding. This method also has several benefits such as high throughput, low temperature, zero-force debonding, and possible selective laser debonding. Adhesive and release layers are key enabling materials for thin glass handling. In addition, the use of a laminator for temporary bonding and laser debonding are included in this study. Based on the excellent fabrication, the thin glass interposer has great potential to be applied in 2.5-D integration applications.
Uneven-Topography-Chip Packing Approach Using Double-Self-Assembly Technology for 3-D Heterogeneous Integration
(2018-02-01)
Shen, Wen-Wei
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Chang, Hsiao-Chun
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Yang, Yu-Tao
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Hu, Yu-Chen
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Chen, Kuan-Neng
Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of mu-pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.
Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology
(2018-08-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Wu, Sheng-Tsai
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Lee, Chia-Hsin
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Huang, Shin-Yi
In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.