Browsing by Author "Sheu, Shyh-Shyuan"

Now showing 1 - 8 of 8

A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing
(2017-06-01)
Chang, Meng-Fan
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Lin, Chien-Chen
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Lee, Albert
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Chiang, Yen-Ning
;
Kuo, Chia-Chen
Existing nonvolatile ternary content-addressable-memory (nvTCAM) suffers from limited word-length (WDL), large write-energy (E-W) and search-energy (E-S), and large cell area (A). This paper develops a 3T1R nvTCAM cell using a single multiple-level cell (MLC)-resistive RAM (ReRAM) device to achieve long WDL, lower E-W and E-S, and reduced cell area. Two peripheral control schemes were developed, dual-replica-row self-timed and invalid-entry power consumption suppression (IEPCS), for the suppression of dc current in 3T1R nvTCAM cells in order to reduce E-S. Two versions of the IEPCS scheme were developed (basic and charge-recycle-controlled) to alter the tradeoff between area overhead and power consumption in the updating of invalid-bits. A 128 b x 64 b 3T1R nvTCAM macro was fabricated using back-end-of-line ReRAM under 90-nm CMOS process. The fabricated MLC-based 3T1R nvTCAM macro achieved sub-1-ns search-delay and sub-6-ns wake-up time with supply voltage of 1 V and WDL = 64 b.
A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time
(2015-01-01)
Chang, Meng-Fan
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Lin, Chien-Chen
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Lee, Albert
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Kuo, Chia-Chen
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Yang, Geng-Hau
A Comprehensive Modeling Framework for Ferroelectric Tunnel Junctions
(2019-01-01)
Huang, Hsin-Hui
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Wu, Tzu-Yun
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Chu, Yueh-Hua
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Wu, Ming-Hung
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Hsu, Chien-Hua
A modeling framework for ferroelectric tunnel junctions (FTJs) that considers nonpolar interfacial layers (ILs), multi-domain polarization, and complete ferroelectric/capacitive/tunneling currents simultaneously is proposed. This model explains both read and write operations including the controversial switching polarities of FTJ. We also provide useful guidelines for optimizing FTJ performance where the location of IL and the effective thickness ratio between ferroelectric and interfacial layers are found to be most critical.
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing
(2016-11)
Chang, Meng-Fan
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Huang, Lie-Yue
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Lin, Wen-Zhang
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Chiang, Yen-Ning
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Kuo, Chia-Chen
This paper outlines the RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) with the following benefits: 1) reduced NVM-stress; 2) reduced ML parasitic load; and 3) suppression of match-line (ML) leakage current from match cells. The RCSD-4T2R cell achieves a 6x reduction in NVM-stress, a 2x increase in maximum wordlength, and a 2x reduction in search delay. In this paper, we also outline two search schemes, referred to as dynamic source-line pulse controlled (DSL-PC) search and dataline-pulse controlled (DL-PC) search, which were developed specifically for the RCSD-4T2R nvTCAM. We fabricated a 128 x 32 b RCSD-4T2R nvTCAM macro with HfO ReRAM using a 180 nm CMOS process. Using the DSL-PC and DL-PC schemes, the measured search delay of the RCSD-4T2R nvTCAM macro was 1.2 ns under typical VDD.
A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application
(2012-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Yao-Jen
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Chen, Peng-Shu
;
Hwang, Yu-Jiau
Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.
Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network
(2019-01-01)
Wu, Ming-Hung
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Hong, Ming-Chun
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Chang, Chih-Cheng
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Sahu, Paritosh
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Wei, Jeng-Hua
This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge
(2019-01-01)
Chang, Chih-Chcng
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Wu, Ming-Hung
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Lin, Jia-Wei
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Li, Chun-Hsien
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Parmar, Vivek
Binary STT-MRAM is a highly anticipated embedded non-volatile memory technology in advanced logic nodes <28 nm. How to enable its in-memory computing (IMC) capability is critical for enhancing AI Edge. Based on the soon-available STT-MRAM, we report the first binary deep convolutional neural network (NV-BNN) capable of both local and remote learning. Exploiting intrinsic cumulative switching probability, accurate online training of CIFAR-10 color images (similar to 90%) is realized using a relaxed endurance spec (switching <= 20 times) and hybrid digital/IMC design. For offline training, the accuracy loss due to imprecise weight placement can be mitigated using a rapid non-iterative training-with-noise and fine-tuning scheme.
Sub-nA Low-Current HZO Ferroelectric Tunnel Junction for High-Performance and Accurate Deep Learning Acceleration
(2019-01-01)
Wu, Tzu-Yun
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Huang, Hsin-Hui
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Chu, Yueh-Hua
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Chang, Chih-Cheng
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Wu, Ming -Hung
This paper presents a unique opportunity of HZO ferroelectric tunnel junction (FTJ) for in-memory computing. The device operates at an extremely low sub-nA current while simultaneously achieving 50-ns fast switching, > 10(7) cycling endurance, > 10-yr retention, minimal variability, and analog state modulation. We analyze an FTJ-based deep binary neural network. It achieves better accuracy and remarkable 702, 101, and 7 x 10(4) times improvements in power, area, and energy area product efficiency compared with those using NVMs with a typical mu A cell current designed for fast memory access.