Browsing by Author "Shie, Bo-Shiuan"

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100-nm IGZO Thin-Film Transistors With Film Profile Engineering
(2014-06-01)
Lin, Horng-Chih
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Shie, Bo-Shiuan
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
100-nm indium-gallium-zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal Al2O3 gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio (>10(7)) and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement.
Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness
(2013-03-01)
Lin, Horng-Chih
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Lin, Cheng-I
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Lin, Zer-Ming
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Shie, Bo-Shiuan
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Huang, Tiao-Yuan
N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C-V characterization, the ionized dopant concentration in the channel is determined to be around 2 x 10(19) cm(-3) and the fixed charge density to be around -6 x 10(12) cm(-2). The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding.
Comparison of Electrical Characteristics of N-type Silicon Junctionless Transistors with and without Film Profile Engineering by TCAD Simulation
(2015)
Tsai, Jung-Ruey
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Lin, Horng-Chih
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Chang, Hsiu-Fu
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Shie, Bo-Shiuan
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Wen, Ting-Ting
Field-effect transistors (FETs) with junctionless (JL) channels have recently attracted much attention for various applications, such as metal-oxide semiconductor thin-film transistors (TFTs) [1], memory devices [2] and Si nanowire TFTs [3, 4]. The Si junctionless (JL) transistors employing high dopant concentration (>= 10(19) cm(-3)) in the source, drain, and nano-scaled channel have been demonstrated to provide excellent electrical characteristics. More recently, film profile engineering (FPE) concept for fabricating downscaled ZnO and IGZO TFTs [5, 6] have been proposed to obtain high-on/off current ratio and great subthreshold swing. Nevertheless, it emphasizes a significant issue of source/drain (S/D) series resistance on the downscaled device performance that needs to be further verified. In this work, electrical performance of downscaled N-type Si JL TFTs with FPE channel and conventional ones will be compared with each other by Sentaurus technology computer aided design (TCAD) simulation [7].
Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach
(2017-03)
Lyu, Rong-Jhe
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Shie, Bo-Shiuan
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Lin, Horng-Chih
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Li, Pei-Wen
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Huang, Tiao-Yuan
We report an exquisite, film- profileengineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9x10(7) and 4.2x10(7), superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometerscale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.
Effects of Gate Dielectric and Process Treatments on the Electrical Characteristics of IGZO TFTs With Film Profile Engineering
(2014-12-01)
Shie, Bo-Shiuan
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Lin, Horng-Chih
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Lyu, Rong-Jye
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
In this paper, high-performance InGaZnO (IGZO) thin-film transistors were fabricated with film-profile-engineering scheme. The impacts of gate dielectric, O-2/Ar ratio during the sputtering of the IGZO, and annealing ambient on the device performance were investigated. It is found that the turn-ON voltage of the device is closely related to the gate dielectric material. For the devices with Al2O3 as the gate dielectric, decent performance in terms of high ON/OFF current ratio (>10(8)), extremely steep subthreshold swing (62 mV/decade), and good mobility (19.8 cm(2)/V.s) is obtained. The influences of O-2/Ar flow ratio are distinct for the devices with Al2O3 gate oxide. Significant improvement in the stability of the devices to the environment is achieved with the anneal done in a low-pressure N-2 ambient.
Film Profile Engineering (FPE): A New Concept for Manufacturing of Short-Channel Metal Oxide TFTs
(2013-01-01)
Lyu, Rong-Jhe
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Lin, Horng-Chih
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Wu, Ming-Hung
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Shie, Bo-Shiuan
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Hung, Hsiang-Ting
A film profile engineering (FPE) concept which utilizes the unique features of various deposition tools to tailor and optimize the profile of the deposited films was demonstrated with the fabricated ZnO TFTs. By implementing the PR trimming technique, high performance devices with L < 100 nm can be readily achieved.
Film-Profile Engineered InGaZnO Thin-Film Transistors With Self-Aligned Bottom Gates
(2015-08-01)
Shie, Bo-Shiuan
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.
Stability of InGaZnO Thin-Film Transistors with Durimide Passivation
(2015)
Shie, Bo-Shiuan
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Chang, Chih-Bin
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Chang, Hao-Chun
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Lin, Horng-Chih
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Huang, Tiao-Yuan
In this work, we investigate the effectiveness of three organic and inorganic materials as the passivation layers in improving the stability of the a-IGZO devices. Two types of organic materials, FH6400 and Durimide 115A, and inorganic PECVD-SiOX were explored in this work. Because of the effective protection from the diffusion of the gas molecules, especially the oxygen molecules, to the active layer, a-IGZO TFTs with the capping of organic passivation layer show good stability under positive bias stress and also show better stability under light illumination with negative bias stress due to low hydrogen content.