Browsing by Author "Shieh, Jia-Min"

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3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
(2012-01-01)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Hsieh, Wei-Shang
;
Tu, Cheng-Hui
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
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Li, Kai-Shin
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Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
A sandwiched buffer layer enabling pulsed ultraviolet- and visible-laser annealings for direct fabricating poly-Si field-effect transistors on the polyimide
(2017-07-10)
Kao, Ming-Hsuan
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Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
;
Lee, Pei-Kang
A sandwiched buffer layer of SiO2/Al/SiO2 enables ultraviolet-laser crystallization and visible-laser activation for direct fabrication of a poly-Si flexible field-effect-transistor (fFET) on polyimides. The buffer layer can produce heat accumulation and laser reflection from the Al/SiO2 interface to facilitate grain growth and contact resistance reduction of poly-Si without damaging the polyimide substrate. The feature size of poly-Si fFET has shrunk to 400nm via laser annealing, with the on/off current-ratio exceeding 5 x 10(6) and a subthreshold swing of 190 mV/dec. Moreover, the transfer characteristics of fFET by tension stress can be maintained until the bending radius reaches over 15 mm. Published by AIP Publishing.
a-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
(2016)
Kao, Ming-Hsuan
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Yang, Chih-Chao
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Wu, Tsung-Ta
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Hsieh, Tung-Ying
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Huang, Wen-Hsieh
Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low I-off and high I-on operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm(2)) under 450 lux indoor illumination, envisions self-power and low cost 3D(+)IC for internet of things.
Approaching conversion limit with all-dielectric solar cell reflectors
(2015-02-09)
Fu, Sze Ming
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Lai, Yi-Chun
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Tseng, Chi Wei
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Yan, Sheng Lun
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Zhong, Yan Kai
Metallic back reflectors has been used for thin-film and wafer-based solar cells for very long time. Nonetheless, the metallic mirrors might not be the best choices for photovoltaics. In this work, we show that solar cells with all-dielectric reflectors can surpass the best-configured metal-backed devices. Theoretical and experimental results all show that superior large-angle light scattering capability can be achieved by the diffuse medium reflectors, and the solar cell J-V enhancement is higher for solar cells using all-dielectric reflectors. Specifically, the measured diffused scattering efficiency (D.S.E.) of a diffuse medium reflector is >0.8 for the light trapping spectral range (600nm-1000nm), and the measured reflectance of a diffuse medium can be as high as silver if the geometry of embedded titanium oxide(TiO2) nanoparticles is optimized. Moreover, the diffuse medium reflectors have the additional advantage of room-temperature processing, low cost, and very high throughput. We believe that using all-dielectric solar cell reflectors is a way to approach the thermodynamic conversion limit by completely excluding metallic dissipation. (C) 2015 Optical Society of America
Characterization and field-emission properties of carbon nanotube arrays in nanoporous alumina template and on blank Si substrate
(2006-11-15)
Yang, Ching-Jung
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Chen, Chih
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Shieh, Jia-Min
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材料科學與工程學系
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Department of Materials Science and Engineering
Ordered carbon nanotube (CNT) arrays were synthesized within anodized aluminum oxide template by thermal decomposition of hydrocarbon precursor with hydrogen ambient at growth temperature as low as 500 degrees C. Excess hydrogen in precursor mixture enables a steady supply of mobile hydrocarbon reactant which promotes facile solid-phase diffusion. The activation energy for CNT growth was determined to be 0.55 eV, a number smaller than 1.02 eV for similar precursor in nitrogen ambient. Moreover, CNTs grown in anodized aluminum oxide nanopores in this low temperature process were found to exhibit unusually high field-emission current of 100 mA/cm(2) at 8 V/mu m. (c) 2006 American Institute of Physics.
Charge-trap non-volatile memories fabricated by laser-enabled low-thermal budget processes
(2015-11-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Pan, Fu-Ming
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Yang, Chih-Chao
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Shen, Chang-Hong
We fabricated charge-trap non-volatile memories (NVMs) using low thermal budget processes, including laser-crystallization of poly-Si thin film, chemical vapor deposition deposition of a stacked memory layer, and far-infrared-laser dopant activation. The thin poly-Si channel has a low defect-density at the interface with the bulk, resulting in a steep subthreshold swing for the NVM transistors. The introduction of the stacked SiO2/AlOxNy tunnel layer and the SiNx charge-trap layer with a gradient bandgap leads to reliable retention and endurance at low voltage for the NVMs. The low thermal budget processes are desirable for the integration of the nano-scaled NVMs into system on panels. (C) 2015 AIP Publishing LLC.
CIGS solar cell integrated with high mobility microcrystalline Si TFTs on 30X40 cm(2) glass panels for self powered electronics
(2012-01-01)
Shen, Chang-Hong
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Shieh, Jia-Min
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Wu, Tsung-Ta
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Huang, Jung Y.
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Huang, Che-Hsuan
For the first time, we report a novel self-powered TFT panel (30X40cm(2)) by integration of sputtering/non-toxic Se vapor selenization copper-indium-gallium-selenide (CIGS) solar cell (conversion efficiency of 8%) and high electron-mobility (172 cm(2)/V-s) micro-crystalline (mu c)-Si TFTs.
CO2 laser annealing of low-hole-concentration polycrystalline germanium for the fabrication of enhancement-mode nMOSFET
(2018-10-01)
Kasirajan, Han Anand
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Huang, Wen-Hsien
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Kao, Ming-Hsuan
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Wang, Hsing-Hsiang
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Shieh, Jia-Min
A p-type polycrystalline Ge (poly-Ge) film processed by UV and CO2 laser annealing reduces the hole concentration from 6 x 10(18) to 2 x 10(16) cm(-3), accompanied by poly-grain growth. The decrease in hole concentration arises from the defect annealing using a CO2 laser, as demonstrated by the changes in the work function, that is, the valence-band maximum (VBM). The laser processes reduce the thermal budget for the fabrication of an enhancement-mode poly-Ge nMOSFET, which has a l(on)/l(off) ratio of 5 x 10(3), a Vth of 2V, and a subthreshold swing of 250 mV/dec., and will be potential fabrication methods for monolithic 3D integrated circuits in the future. (C) 2018 The Japan Society of Applied Physics
DC and high-frequency characteristics of trigate polycrystalline-silicon thin-film transistors with different layout geometries
(2019-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Shiao, Yu-Shao Jerry
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Lin, Chuang-Ju
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Huang, Guo-Wei
In this paper, we present the dc and high-frequency characteristics of trigate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) for RF applications. Trigate TFTs were fabricated using a 3D-IC process and designed with a multi-finger gate and multi-channel configuration. To obtain an optimal device design guideline, different source/drain (S/D) extension dimensions and channel layouts are investigated. We find that devices with a shorter or wider extension have higher cutoff frequencies (f(T)) and maximum oscillation frequencies (f(max)) owing to their lower S/D resistances. In addition, the high-frequency performance can be further improved by adopting the tapered channel structure, where the channel width increases gradually from the source to the drain. For the optimal device designs, the values of f(T) and f(max) are around 25 GHz and 30 GHz, respectively. The high f(T) and f(m)(ax) as well as excellent gate controllability in our devices indicate the trigate poly-Si TFT could be a suitable candidate for low-cost RFIC applications. (C) 2019 The Japan Society of Applied Physics
Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
(2019-12-01)
Chung, Yun-Yan
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Lu, Kuan-Cheng
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Cheng, Chao-Ching
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Li, Ming-Yang
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Lin, Chao-Ting
For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10(6), a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
Design, fabrication, and characterization of Si-based ARROW photonic crystal bend waveguides and power splitters
(2012-08-20)
Chen, Jian-Hua
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Huang, Yang-Tung
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Yang, Yu-Lin
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Lu, Ming-Feng
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Shieh, Jia-Min
Silicon-based (Si-based) photonic crystal waveguide based on antiresonant reflecting optical waveguide (ARROW PCW) structures consisting of 60 degrees bends and Y-branch power splitters were designed and first efficiently fabricated and characterized. The ARROW structure has a relatively large core size suitable for efficient coupling with a single-mode fiber. Simple capsule-shaped topography defects at 60 degrees photonic crystal (PC) bend corners and Y-branch PC power splitters were used for increasing the broadband light transmission. In the preliminary measurements, the propagation losses of the ARROW PC straight waveguides lower than 2 dB/mm with a long length of 1500 mu m were achieved. The average bend loss of 60 degrees PC bend waveguides was lower than 3 dB/bend. For the Y-branch PC power splitters, the average power imbalance was lower than 0.6 dB. The results show that our fabricated Si-based ARROW PCWs with 60 degrees bends and Y-branch structures can provide good light transmission and power-splitting ability. (c) 2012 Optical Society of America
DEVICE MODELING OF A MICROMORPH TANDEM SOLAR CELL USING AMPS-1D
(2010)
Huang, J. Y.
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Hsu, C. W.
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Shieh, Jia-Min
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Yu, Peichen
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光電工程學系
This work first theoretically optimize the amorphous (a-Si:H) and the microcrystalline (mu c-Si:H) devices characteristics, and then perform studies for micromorph tandem solar cells. The studies calculated by AMPS-1D show that the TCO work function has obvious influence on the open-circuit voltage. Moreover, the power conversion efficiency of an a-Si:H cell is optimized by changing the absorber's layer thickness and mobility gap. Furthermore, a critical doping concentration of mu c-Si:H films limiting the barrier height of a grain boundary (GB) is observed. After optimizing sub cell mutually, we combine the individual junctions to construct a micromorph cell which has an efficiency of 9.24%.
Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability
(2013-11-11)
Chiou, Uio-Pu
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Shieh, Jia-Min
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Yang, Chih-Chao
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Huang, Wen-Hsien
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Kao, Yo-Tsung
We fabricated nano-crystalline Si (nc-Si: H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (mu(FE)) and adjustable threshold voltages (V-th). The nc-Si: H channel and source/drain (S/D) of the multilayered TFT were deposited at 375 degrees C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high mu(FE) of 370 cm(2) /V-s, a steep subthreshold slope of 90 mV/decade, and a low V-th of -0.64 V. When biased with the double-gate driving mode, the device shows a tunable V-th value extending from -1V up to 2.7 V. (C) 2013 AIP Publishing LLC.
Down Shifted Converssion for Enhanceed HIT SSolar Cell Efficiency
(2017-01-01)
Lin, Albert S.
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Parashar, Parag
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Huang, Wei-Ming
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Huang, Yi-Wen
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Jian, Ding-Rung
In this work, HIT solar cell is incorporated with the luminescent down-shifting (LDS) mechanism for the incident solar spectrum. The heterojunction with intrinsic thin-layer(HIT) solar cell is highly efficient, low temperature (200 C), low cost, and highly symmetrical device. Nevertheless, the carrier collection efficiency is low for the short wavelength solar photons due to the surface recombination. Here, a thin phosphor layer is spray coated on the top of HIT solar cells for the luminescent down-shifting of high energy photons and thus enhanced external quantum efficiency (EQE) for the device for lambda=300nm-450nm is observed.
Effect of polyethylene glycol additives on pulse electroplating of SnAg solder
(2008-02-01)
Chen, Hsiao-Yun
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Chen, Chih
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Wu, Pu-Wei
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Shieh, Jia-Min
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Cheng, Shing-Song
Eutectic Sn-3.5wt.%Ag alloy is one of the most promising lead-free solders in low temperature processes for wafer bumping. Near eutectic composition of deposited alloy films could be readily acquired by pulse electroplating with a proper combination of active ingredients including K4P2O7, KI, Sn2P2O7, and AgI, as well as polyethylene glycol (PEG), with molecular weights of 200, 600, 2,000, and 4,000, as an inhibitive agent. Pulse electroplating was carried out with current in alternating polarity to conduct electroplating and electropolishing sequentially. As a result, alloy films with grains of less than 1 mu m and uniform surface morphology can be obtained. The addition of PEG was necessary for the stabilization of the plating baths to promote a wider process window for the desirable eutectic composition. Electrochemical characterization established that PEG with molecular weight of 4,000 exhibited the strongest inhibition behavior. In contrast, PEG with molecular weight of 200 demonstrated the least interference. Energy dispersive X-ray and differential scanning calorimeter data confirmed the formation of eutectic alloy as a function of deposition current density. X-ray diffraction results indicated that a biphasic structures of beta-Sn and epsilon-Ag3Sn was present in the as-deposited film.
Embedded biomimetic nanostructures for enhanced optical absorption in thin-film solar cells
(2011-07-04)
Tsai, Min-An
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Han, Hao-Wei
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Tsai, Yu-Lin
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Tseng, Ping-Chen
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Yu, Peichen
Light-management is critical to thin film solar cells due to their usually limited optical absorption in the active layer. Conventional approaches involve employing separate techniques for anti-reflection and light trapping. Here, we demonstrate an embedded biomimetic nanostructure (EBN) that achieves both effects for hydrogenated amorphous silicon (a-Si: H) solar cells. The fabrication of EBNs is accomplished by patterning an index-matching silicon-nitride layer deposited on a glass substrate using polystyrene nanospheres lithography, followed by reactive ion etching. The profile of EBN is then reproduced layer by layer during the deposition of a-Si: H cells. We show that a solar cell with an optimized EBN exhibits a broadband enhanced external quantum efficiency due to both antireflection and light-trapping, with respect to an industrial standard cell using an Asahi U glass substrate which is mostly optimized for light trapping. Overall, the cell with an optimized EBN achieves a large short-circuit current density of 17.74 mA/cm(2), corresponding to a 37.63% enhancement over a flat control cell. The power conversion efficiency is also increased from 5.36% to 8.32%. Moreover, the light management enabled by the EBN remains efficient over a wide range of incident angles up to 60 degrees, which is particularly desirable for real environments with diffused sun light. The novel patterning method is not restricted to a-Si:H solar cells, but is also widely applicable to other thin film materials. (C) 2011 Optical Society of America
Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing
(2017-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Kao, Ming-Hsuan
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Shen, Chang-Hong
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Huang, Tzu-En
A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 x 10(19) cm(-3) and a narrow Raman FWHM of 3.9 cm(-1). Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I-on/I-off ratio of 6 x 10(4), V-th of % -0.3 V, and a subthreshold swing of 237mV/dec at V-d of 1V and DIBL of 101mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V-th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics. (C) 2017 The Japan Society of Applied Physics
Enhanced fight transmission for Si solar cells using anti-reflector of mesoporous silica with low refractive index
(2007)
Shieh, Jia-Min
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Wang, Chao-Kei
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Wu, Shich-Chuan
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Ni, Wei-Xin
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Kuo, Hao-Chung
Mesoporus silica dielectrics, which revealed low refractive index (n similar to 1.27), were introduced together with Si3N4 layers to be double-layer-based graded-refractive-index ant-reflectors for silicon solar-cells. Enhanced solar-light transmission increased conversion efficiency of Si solar panels by 20%.
Enhanced green laser activation by antireflective gate structures in panel transistors
(2008-02-11)
Shieh, Jia-Min
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Chen, Chih
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Lin, Yu-Ting
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Pan, Ci-Ling
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材料科學與工程學系
Antireflective gate structures of polycrystalline silicon (poly-Si) and silicon dioxide films enable postimplantation green continuous-wave laser annealing of all Si regions of green laser-crystallized panel Si transistors. About 40% of the incident laser-energy penetrates to the channels, owing to antireflective gate structures with the absorptive gate poly-Si, while 65% of the incident laser-energy enters the source/drain regions because of Fresnel reflections at the air/source (drain) interfaces. Such inverted laser-energy profiles and ascendant defect distributions along the channels/junctions/contact regions, yielded continuous, improved epilike Si microstructures over the entire active layer. The electron mobility of the transistors, 620 cm(2)/V s, approaches that of integrated-circuits transistors. (C) 2008 American Institute of Physics.