Browsing by Author "Shieh, MS"

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A novel dynamic threshold voltage MOSFET (DTMOS) using heterostructure channel of Si1-yCy interlayer
(2005-10-01)
Shieh, MS
;
Chen, PS
;
Tsai, MJ
;
Lei, TF
;
電子工程學系及電子研究所
We have demonstrated the fabrication of dynamic threshold voltage MOSFET (DTMOS) using the Si1-yCy(y = 0.005) incorporation inerlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si1-yCy interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. This novel Si1-yCy channel heterostructure MOSFET exhibits higher transconductance and turn on current.
Characterization of polysilicon thin-film transistors with asymmetric source/drain implantation
(2005-08-01)
Shieh, MS
;
Lin, YJ
;
Yu, CM
;
Lei, TF
;
電子工程學系及電子研究所
The effect of asymmetry tilt angle ion implantation on polysilicon thin-film transistors (TFTs) device characteristics are investigated. This asymmetric source/drain (S/D) TFTs structure exhibits low leakage current and suppressed kink effect due to the relief of higher electric field near the drain junction side. It is shown that the optimal implantation tilt angle is 30 degrees in our annealing condition. And the anomalous off-state current is more than two orders of magnitude lower than that of the conventional TFTs. By well controlled the LDD region, this structure can act as a conventional structure in the on-state and the turn-on current will not be degraded. Besides, the device under severe hot carrier bias stress shows better hot carrier endurance. (c) 2005 Elsevier B.V. All rights reserved.
Electrical characteristics and reliability of multi-channel polycrystalline silicon thin-film transistors
(2006-04-01)
Shieh, MS
;
Sang, JY
;
Chen, CY
;
Wang, SD
;
Lei, TF
We demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) with different numbers of channel stripes.-The device's electrical characteristics, such as on-current, threshold voltage, and subthreshold swing, were improved by increasing the number of channel stripes due to the enhancement of gate control. However, the electric field strength near the drain side was enlarged in multi-channel structures, causing severe impact ionization. The degradation of device's reliability under various electrical stress conditions was suggested.
Improvement of polysilicon oxide integrity using NF3-annealing
(2000-06-15)
Yang, WL
;
Shieh, MS
;
Chen, YM
;
Chao, TS
;
Liu, DG
We report a method to improve the polysilicon oxide integrity by using NF3-annealing. Incorporating with stronger Si-N and Si-F bonds at the polysilicon/polyoxide interface, significant improvements are found in terms of roughness, breakdown strength, charge-to-breakdown, and stress-induced-leakage-current.
Retardation in the chemical-mechanical polish of the boron-doped polysilicon and silicon
(2000-05-01)
Yang, WL
;
Cheng, CY
;
Tsai, MS
;
Liu, DG
;
Shieh, MS
;This letter reports on the chemical-mechanical polishing (CMP) of boron doped polysilicon and silicon. Successive polishing was carried out to investigate how the removal rate correlates to the boron concentration as a function of depth in the polysilicon and crystalline silicon. It is found that the removal of baron-doped samples is significantly retarded and strongly correlated with the doping concentration. To the author's knowledge, this work is the first report discussing the retardation effect of boron in the Si-CMP process, This effect is attributed to the activated dopant atoms which are conjectured to inhibit the hydrolysis reaction of Si-Si bonding in the alkaline aqueous solution. In our study, the retardation effect is evident for the boron concentration higher than 5 x 10(18) cm(-3). As a consequence, it may become an issue in CMP process for those layers of selected or complemented doping.
The CMP process and cleaning solution for planarization of strain-relaxed SiGe virtual substrates in MOSFET applications
(2006)
Shieh, MS
;
Chen, PS
;
Tsai, MJ
;
Lei, TF
;
電子工程學系及電子研究所
The effects of different polishing pads and slurry solid contents on the SiGe chemical mechanical polish (CMP) process were investigated. By optimizing the polishing conditions, a smooth strained-Si surface on a flattened Si0.8Ge0.2 buffer layer of 0.6 nm can be achieved. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. There was about 10% current enhancement of the optimal cleaning conditions, showing high performance in particle removal, metallic cleaning, and electrical characteristics. (c) 2005 The Electrochemical Society.