Browsing by Author "Shieh, TL"

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Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
(2001)
Ker, MD
;
Jiang, HC
;
Peng, JJ
;
Shieh, TL
;
電子工程學系及電子研究所
A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.