Browsing by Author "Shih, An-Shih"

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First Experimental Demonstration and Mechanism of Abnormal Palladium Diffusion Induced by Excess Interstitial Ge
(2018-11-01)
Chou, Chen-Han
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Shih, An-Shih
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Yu, Shao-Cheng
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Lin, Yu-Hsi
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Tsai, Yi-He
This letter represents the first direct experimental demonstrations and mechanism proposal regarding abnormal palladium diffusion into germanium (Ge). Our experiments indicated that excess Ge atoms among palladium germanide alloy formation indirectly induce the abnormal out-diffusion of mass palladium atoms into Ge. Consequently, palladium germanide alloy on both n-type and p-type Ge form ohmic-like Schottky junctions. To identify this phenomenon, first-principle calculations and technology computer-aided design simulation were used to evaluate the electrical influence of palladium atoms in Ge. We discovered that the activated palladium atoms in Ge induce large midgap bulk-trap states, which contribute to a severe increment of trap-assisted tunneling current at the palladium germanide/Ge junction.
Improving Thermal Stability and Interface State Density of High-kappa Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium
(2016-11)
Tsai, Yi-He
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Chou, Chen-Han
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Shih, An-Shih
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Jau, Yu-Hau
;
Yeh, Wen-Kuan
We propose a new HfGeOx interfacial layer (IL) for the high-kappa gate-stacks on p-type germanium substrate with improved thermal stability as compared with that of conventional GeOx IL. We inserted an additional HfO2 layer after the formation of GeOx in the HfO2/Al2O3/GeOx/Ge gate-stack by using plasma-enhanced atomic layer deposition. Through the use of post-deposition annealing and post-metal annealing, the new system exhibited greater thermal immunity and was stable up to 600 degrees C. We speculate that the improvement originates from the formation of HfGeOx through the combination of HfO2 and GeOx, according to the thermodynamic data. By incorporating Hf into interfacial layer, the fabricated high-kappa gate-stack with an equivalent oxide thickness of 1.2 nm, a low interface states density (D-it) of approximately 3.3 x 10(11) eV(-1) cm(-2), and an impressive gate leakage current of approximately 2.2 x 10(-6) A/cm(2) at VFB-1V.
Incorporating Yttrium into a GeO Interfacial Layer with HfO2-Based Gate Stack on Ge
(2018-01-01)
Chou, Chen-Han
;
Lu, Yu-Hong
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Tsai, Yi-He
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Shih, An-Shih
;
Yeh, Wen-Kuan
In this study, we employed the electrical and material properties of various interfacial layers (ILs) such as GeO and YGeO on a Ge substrate. First, capacitors using various ILs with HfO2-based gate stacks were developed. The capacitor using YGeO IL exhibited a low interface state density (D-it) of 2.5 x 10(11) eV(-1)cm(-2) and an equivalent oxide thickness of 1.8 nm. Next, a reliability test for constant voltage stress was conducted for further studying the YGeO ILs. The capacitors with YGeO ILs presented higher immunity for Dit degradation. Further, to understand the material properties of various ILs, a simple experiment on capping a Si chip on GeO or YGeO/Ge samples through high-temperature annealing was conducted. We observed that Ge and GeO vapors can be absorbed by Si and detected through X-ray photoelectron spectroscopy (XPS). XPS spectra of Si chips capped on GeO IL presented obvious features of Ge and GeO through annealing at 500 degrees C; however, the XPS spectra of Si chips capped on YGeO IL presented no features, indicating that YGeO ILs had higher thermal stability than GeO ILs. To further analyze the HfO2-based gate stacks with various ILs, Ge diffusion into a high-k HfO2 layer was investigated through angle-resolved XPS. We observed that YGeO ILs with HfO2-based gate stacks can reduce Ge diffusion into a HfO2 layer. (C) 2018 The Electrochemical Society.