Browsing by Author "Shih, Chang-Fu"

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An analysis of the ceiling height requirement for a large-scale semiconductor fab
(2010)
Wu, Muh-Cherng
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Shih, Chang-Fu
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Chen, Chen-Fu
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工業工程與管理學系
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Department of Industrial Engineering and Management
This paper proposes the proposition that the fab ceiling height may become a bottleneck for throughput in a large-scale semiconductor fab. To justify the proposition, we propose a systematic approach for the design of the fab ceiling height. In this approach, we develop a queuing network model to evaluate the cycle time performance of a fab design under a target throughput. This queuing network model is adapted from Connor et al. [1996. A queueing network model for semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing, 9 (3), 412-427] by additionally treating the transportation facilities as finite-capacity resources. Numerical experiments were carried out. The results indicate that a large-scale fab with an inappropriate ceiling height may limit the installation of transportation capacity, which, in turn, limits the utilisation of tool capacity, and thus lowers the fab throughput that can be achieved.
An efficient approach to cross-fab route planning for wafer manufacturing
(2009-10-01)
Wu, Muh-Cherng
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Shih, Chang-Fu
;
Chen, Chen-Fu
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工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper proposes an efficient approach to solve a cross-fab route planning problem for semiconductor wafer manufacturing. A semiconductor company usually adopts a dual-fab strategy. Two fab sites are built neighbor to each other to facilitate capacity-sharing. A product thus may be produced by a cross-fab route; that is, some operations of a product are manufactured in one fab and the other operations in the other fab. This leads to a cross-fab routing planning problem, which involves two decisions-determining the cut-off point of the cross-fab route and the route ratio for each product-in order to maximize the throughput subject a cycle time constraint. A prior study has proposed a method to solve the cross-fab route planning problem; yet it is computationally extensive in solving large scale cases. To alleviate this deficiency, we proposed three enhanced methods. Experiment results show that the best enhanced method could significantly reduce the computational efforts from about 13 h to 0.5 h, while obtaining a satisfactory solution. (C) 2009 Elsevier Ltd. All rights reserved.
Route planning for two wafer fabs with capacity-sharing mechanisms
(2009)
Wu, Muh-Cherng
;
Chen, Chen-Fu
;
Shih, Chang-Fu
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper formulates and solves a route planning problem for semiconductor manufacturing. In order to quickly respond to rising demand, a semiconductor company usually adopts a dual-fab strategy to expand capacity. That is, two fab sites are built as neighbours and can easily share capacity. Through the capacity-sharing design, a product may be produced by a cross-fab route. That is, some operations of a product are carried out in one fab and the other operations in the other fab. This leads to a routing planning problem, which involves two decisions-determining the cut-off point of the cross-fab route and the route ratio for each product-in order to maximise the throughput subject to a cycle time constraint. An LP-GA method is proposed to solve the route planning problem. We first use the LP module to make the cut-off point decisions, and proceed to use the GA module for making the decision on the route ratio. Experimental results show that the LP-GA method significantly outperforms other methods.