Browsing by Author "Shih, Che-Hua"

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Accelerating Dynamic Peak Power Analysis Using An Essential-Signal-Based Methodology
(2011)
Shih, Che-Hua
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Yen, Chia-Chih
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Lin, Shen-Tien
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Lin, Hermes
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Jou, Jing-Yang
Accurate peak power measurement requires detailed switching and delay information for each signal over the entire simulation. Performing a full signal dump and power calculation for a long simulation run usually spends a large amount of time and disk space. In this paper, we propose an Essential-signal-based methodology which only performs power analysis over a small subset of the original simulation but still acquires the true peak power value. Experimental results show that the proposed methodology significantly decreases both time (about 18 X speedup) and disk space usage (about 87% reduction) against the traditional power analysis flow.
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM
(2009-05-01)
Shih, Che-Hua
;
Huang, Juinn-Dar
;
Jon, Jing-Yang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Verifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation. approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.
Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
(2011)
Lee, Chi-Hui
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Shih, Che-Hua
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Huang, Juinn-Dar
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Jou, Jing-Yang
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電子工程學系及電子研究所
This paper presents a formal method for equivalence checking between the descriptions before and after scheduling in high-level synthesis (HLS). Both descriptions are represented by finite state machine with datapaths (FSMDs) and are then characterized through finite sets of paths. The main target of our proposed method is to verify scheduling employing code transformations - such as speculation and common subexpression extraction (CSE), across basic block (BB) boundaries - which have not been properly addressed in the past. Nevertheless, our method can verify typical BB-based and path-based scheduling as well. The experimental results demonstrate that the proposed method can indeed outperform an existing state-of-the-art equivalence checking algorithm.
FSM-Based Formal Compliance Verification of Interface Protocols
(2010-09-01)
Shih, Che-Hua
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Yang, Ya-Ching
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Yen, Chia-Chih
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Huang, Juinn-Dar
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Jou, Jing-Yang
Verifying whether a building block conforms to a specific interface protocol is one of the important steps in a platform-based system-on-a-chip design methodology. There are limitations for most of the existing methods for interface protocol compliance verification. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this paper, we propose a novel approach for interface protocol compliance verification. The properties of the interface protocol are first specified as a specification FSM. Then the compliance of interface logic is formally verified at the higher FSM level so that the required memory and runtime can be greatly reduced. Finally, it is shown theoretically and experimentally that the proposed algorithm possesses acceptably low time complexity for practical applications.
FSM-based transaction-level functional coverage for interface compliance verification
(2006)
Su, Man-Yun
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Shih, Che-Hua
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Huang, Juinn-Dar
;
Jou, Jing-Yang
;
電子工程學系及電子研究所
Interface compliance verification plays a very important role in modern SoC designs. In order to perform a quantitative analysis of simulation completeness, adequate coverage metrics are mandatory. In this paper, we propose a finite state machine (FSM) based transaction-level functional coverage methodology for interface compliance verification. A language, State-Oriented Language (SOL), is developed to specify functional transactions mainly at the higher FSM level instead of lower logic or signal level. By utilizing SOL, it is simple and rigorous to specify interesting transactions from the specification FSM of the target interface protocol. Experimental results show that the proposed methodology can effectively improve the verification quality as well as increase the efficiency of regression verification.