Browsing by Author "Shih, PS"

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A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition
(1999-08-01)
Shih, PS
;
Chang, CY
;
Chang, TC
;
Huang, TY
;
Peng, DZ
We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFT's), The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) oxide performed at 23 degrees C, Devices fabricated with the new process exhibit a lower leakage current and a better ON/OFF current ratio than non-LDD control devices. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be quite promising for future high-performance poly-Si TFT fabrication.
A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain
(2003-08-01)
Zan, HW
;
Chang, TC
;
Shih, PS
;
Peng, DZ
;
Kuo, PY
With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.
A W-spacer GOLD TFT with high performance and high reliability
(2002-09-26)
Zan, HW
;
Peng, DZ
;
Shih, PS
;
Chang, TC
;
Liu, PT
In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state. (C) 2002 Elsevier Science Ltd. All rights reserved.
Analysis of narrow width effects in polycrystalline silicon thin film transistors
(2003-01-01)
Zan, HW
;
Chang, TC
;
Shih, PS
;
Peng, DZ
;
Huang, TY
In this study, narrow width effects of polycrystalline silicon thin film transistors (poly-Si TFTs) are investigated. With reducing channel width, TFT characteristics such as. mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow width effects, a physically-based model is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and-tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found that the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area.
Annealing effects on the interfacial reactions of Ni on Si0.76Ge0.24 and Si1-x-yGexCy
(2000-01-01)
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
;
Pan, FM
Interfacial reactions of Ni/Si0.76Ge0.24 and Ni/Si1-x-yGexCy by vacuum annealing and pulsed KrF laser annealing were studied. Upon annealing at a temperature of 200-600 degrees C Ge segregation occurred with the extent becoming more severe at higher temperatures. The temperatures at which phase transformation and the agglomeration structure occurred were higher for Ni/Si1-x-yGexCy than for Ni/Si0.76Ge0.24. Upon pulsed KrF laser annealing the agglomeration structure was considerably improved, however, the retardation of phase transformation in the Ni/Si1-x-yGexCy system still occurred. C accumulation around the original amorphous/crystal interface formed by Cf implantation played a significant effect on delaying the phase transformation. For the Ni/Si0.76Ge0.24 and Ni/Si1-x-yGexCy samples annealed at 0.2 J/cm(2) for 20 and 30 pulses, respectively, smooth Ni(Si0.76Ge0.24)(2) and Ni(Si1-x-yGexCy)(2) films could be grown, meanwhile Ge segregation and strain relaxation of the unreacted Si0.76Ge0.23 films were effectively suppressed. (C) 2000 American Vacuum Society. [S0734-2101(00)04301-3].
Characterization and reliability of lightly-doped-drain polysilicon thin-film transistors with oxide sidewall spacer formed by one-step selective liquid phase deposition
(2000-10-01)
Shih, PS
;
Chang, TC
;
Huang, TY
;
Yeh, CF
;
Chang, CY
We have proposed and successfully demonstrated a novel process for fabricating a lightly doped drain (LDD) polysilicon thin-film transistor (poly-Si TFT). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) at 23 degreesC. In contrast with conventional methods, this new process does not require an additional photolithographic step for defining the non-self-aligned offset gate, or the deposition of an oxide layer and subsequent etch-back to form the: self-aligned sidewall spacer. Devices fabricated by the new process have a lower leakage current and a better ON/OFF current ratio, compared with non-LDD control devices. The new device also shows excellent current saturation characteristics at high bias and better has hot-carrier endurance. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be promising for future high-performance poly-Si TFT fabrication.
Characterization of Si1-x-yGexCy films grown by C+ implantation and subsequent pulsed laser annealing
(1999-07-15)
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
;
Pan, FM
Epitaxial Si1-x-yGexCy films have been grown by C+ implantation into Si0.76Ge0.24 films with a dose of 1.0 x 10(16)/cm(2) and subsequent pulsed KrF laser annealing at an energy density of 0.3-1.6 J/cm(2). Upon laser annealing Ce segregation to the film surface and diffusion to the underlying Si appeared at energy densities above 0.8 J/cm(2) and 1.4 J/cm(2), respectively while the depth profiles of C remained nearly unchanged as in the as-implanted Si1-x-yGeyCy film. Concurrently, no SiC and twin were observed. The amount of C incorporated into substitutional sites initially increased with the energy density in the range of 0.3-1.0 J/cm(2), and then saturated at an energy density of 1.0-1.6 J/cm(2). For the Si1-x-yGexCy films grown at 1.0 J/cm(2) for 5 and 20 pulses SiC was formed with its amount increasing with the pulse number because of C segregation to the film surface and the original amorphous/crystal interface where the EOR defects were present. For the Si1-x-yGexCy films grown at energy densities below 1.0 J/cm(2) the reduction of tensile stress mainly resulted from the effect of substitutional carbon incorporation. (C) 1999 Elsevier Science S.A. All rights reserved.
Comparison of poly-Si films deposited by UHVCVD and LPCVD and its application for thin film transistors
(2002-09-26)
Peng, DZ
;
Zan, HW
;
Shih, PS
;
Chang, TC
;
Lin, CW
The ultra-high vacuum chemical vapor deposition (UHVCVD) system can deposit poly-Si film without any laser or furnace annealing. The uniformity of threshold voltage and mobility is superior to that deposited by low-pressure chemical vapor deposition (LPCVD) system. However, due to the deposition in polycrystalline phase for UHVCVD, the film surface is rough and results in low field effect mobility compared to that obtained by LPCVD using disilane (Si2H6) in amorphous phase followed by solid phase crystallization (SPC). The on-off current ratio for UHVCVD deposited poly-Si thin film transistors (TFTs) is approximately one order smaller, however, the leakage current for LPCVD SPC TFTs is higher. In this experiment, NH3 was introduced to both of the two samples to improve the device performance. It can be shown that improvements on device characteristics are more significant for UHVCVD deposited poly-Si TFTs, e.g. threshold voltage decreased dramatically and the on-off current ratio improved by two orders of magnitude. (C) 2002 Elsevier Science Ltd. All rights reserved.
Dimensional effects on the drain current of n- and p-channel polycrystalline silicon thin film transistors
(2000-07-01)
Shih, PS
;
Zan, HW
;
Chang, TC
;
Huang, TY
;
Chang, CY
N-channcl and p-channel polysilicon thin him transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.
Dimensional effects on the reliability of polycrystalline silicon thin-film transistors
(2000-08-01)
Zan, HW
;
Shih, PS
;
Chang, TC
;
Chang, CY
;
電子工程學系及電子研究所
We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I-min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated SI-H bonds. (C) 2000 Elsevier Science Ltd. All rights reserved.
Effects of an interposed Mo layer on the interfacial reactions of Ti/Si0.76Ge0.24 by rapid thermal annealing and pulsed laser annealing
(2000-10-01)
Huang, JC
;
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
The thickness effect of an interposed Mo layer between Ti and Si0.76Ge0.24 films on the lowering of the formation temperature of C54 (Ti, Mo)(Si1-xGex)(2), thereby reducing Ge segregation and agglomeration of the C54 (Ti, Mo)(Si1-xGex)(2) films, is studied. Upon rapid thermal annealing, the interposed Mo layer can significantly reduce the formation temperature of C54 (Ti, Mo)(Si1-xGex)(2); however, the amount of reduction decreases with the Mo thickness. The electron/atom ratio seems to be one of the important factors in the lowering of the formation temperature of C54 (Ti, Mo)(Si1-xGex)(2). For the samples having an interposed Mo layer 0.5 nm thick a smooth C54 (Ti, Mo)(Si1-xGex)(2) film without Ge segregation can be grown after annealing at a temperature of 625-650 degreesC. For pulsed KrF laser annealing the rapid melt/solidification process allows only growth of C40 Ti(Si1-xGex)(2) or C40 (Ti, Mo)(Si1-xGex)(2) even though an interposed Mo layer is introduced into the Ti/Si0.76Ge0.24 samples, indicating that upon pulsed laser annealing the kinetic effect can dominate over the thermodynamic effect.
Effects of Mo-free C40Ti(Si1-xGex)(2) precursors and the thickness of an interposed Mo layer on the enhanced formation of C54Ti(Si1-xGex)(2)
(1999-11-29)
Luo, JS
;
Huang, JC
;
Lin, WT
;
Chang, CY
;
Shih, PS
The effects of Mo-free C40 Ti(Si1-xGex)(2) precursors and the thickness of an interposed Mo layer between Ti films and Si0.76Ge0.24 substrates on the lowering of formation temperature of C54 Ti(Si1-xGex)(2) were studied. Metastable C40 Ti(Si1-xGex)(2) precursors were grown by pulsed KrF laser annealing. Upon rapid thermal annealing, the Mo-free C40 phase could not be directly transformed to the C54 phase without going through the C49 phase. When the thickness of the interposed Mo layer increased, up to 2.5 nm, the temperature at which the C54 phase was initially formed changed from 750 to 600 and then to 650 degrees C. The present result showed that with increasing Mo concentration in the reacted layer, the phase stability shifted from C54 to C40 and no C49 was observed. It seems that apart from the C40 template mechanism, the electron/atom ratio also plays an important role in the enhanced formation of the C54 phase. (C) 1999 American Institute of Physics. [S0003-6951(99)02048-3].
High performance thin-film transistors with low-high-low band gap engineering
(1998)
Chang, CY
;
Lee, YS
;
Shih, PS
;
Lin, CW
;
電子工程學系及電子研究所
A novel high-performance thin-film transistor (TFT) with low-high-low band gap structure is proposed. We propose a novel device structure combined with low-band-gap materials (microcrystalline Si, mu c-Si:H) for the channel region, high-band-gap materials (hydrogenated amorphous silicon, a-Si:H) for the source and drain offset regions, and heavily doped low-bandgap materials (n(+) a-Si:H) for ohmic contact of source and drain electrodes. We found that, as compared to a-Si:H TFT device with conventional inverted-stagger structures, the device with low-band-gap materials in the channel (e.g. mu c-Si:H) which possesses high conductance can effectively improve the film quality of initial growth active layer near the gate insulator interface and the grown layer. Hence the TFT device parameters such as field effect mobility, threshold voltage, subthreshold swing and ON-current have been significantly improved. This proposed novel structure with high-band-gap material is used to prevent the band to band tunneling and alleviate the high OFF-current in conventional mu c-Si:H thin-film transistors. The proposed high performance TFTs with low-high-low band gap structure will have a great impact in application to high resolution thin-film transistor liquid-crystal displays (TFT-LCDs) and active-matrix liquid-crystal displays (AMLCDs).
Improvements of amorphous-silicon inverted-staggered thin-film transistors using high-temperature-deposited Al gate with chemical mechanical polishing
(2000-05-01)
Shih, PS
;
Chang, TC
;
Liang, CY
;
Huang, TY
;
Chang, CY
Chemical mechanical polished Al (CMP-Al) films deposited at various temperatures were explored as the gate electrodes of amorphous- silicon (a-Si:H) inverted-staggered thin-film transistors (TFTs) for the first time. Although the surface roughness of the as-deposited Al films increased with increasing deposition temperature, Al films deposited at higher temperature were more robust to hillock formation during subsequent annealing. To take advantage of the better hillock suppression properties, CMP is employed to reduce the inherently large surface roughness of these high-temperature-deposited Al films. Our results show that the electrical characteristics of the TFTs are significantly improved. Specifically, the threshold voltage is reduced from 2.37 to 1.43 V, the mobility is improved from 0.32 to 1.36 cm(2)/V s, and the subthreshold swing is improved from 0.72 to 0.58 V/decade as the Al deposition temperature is increased from 25 to 400 degrees C. (C) 2000 The Electrochemical Society. S1099-0062(99)10-107-X. All rights reserved.
Interfacial reactions of Co/Si0.76Ge0.24 and Co(Si0.76Ge0.24)/Si0.76Ge0.24 by pulsed KrF laser annealing
(1999-08-01)
Luo, JS
;
Hang, YL
;
Lin, WT
;
Chang, CY
;
Shih, PS
Interfacial reactions of Co/Si0.76Ge0.24 and Co(Si0.76Ge0.24)/Si0.76Ge0.24 by pulsed KrF laser annealing as a function of energy density and pulse number were studied. For the Co/Si0.76Ge0.24 samples annealed at an energy density of 0.2-0.6 J/cm(2), three germanosilicide layers, i.e., amorphous structure and/or nanocrystal, Co(Si1-xGex), and Co(Si1-xGex)(2), were successively formed along the film-depth direction. At 0.3 J/cm(2) Ge segregated to the underlying Si0.76Ge0.24 film, inducing strain relaxation in the residual Si0.76Ge0.24 film. At 0.8 J/cm(2) the reacted region was mostly transformed to a single layer of Co(Si1-xGex)(2), whereas Ge further diffused to the Si substrate. At 1.0 J/cm2, constitutional supercooling appeared. Even the Co(Si0.76Ge0.24) film used as the starting material for laser annealing could not prevent the occurrence of constitutional supercooling at energy densities >1.6 J/cm2. The energy densities at which Co(Si1-xGex) transformation to Co(Si1-xGex)(2), Ge segregation to the underlying Si, and constitutional supercooling occurred were higher for the Co(Si0.76Ge0.24)/Si0.76Ge0.24 system than for the Co/Si0.76Ge0.24 system. Higher energy density and/or pulse number enhanced the growth of Co(Si,,Ge,), film. In the present study, the Co/Si0.76Ge0.24 samples subjected to annealing at 0.2 J/cm(2) for 20 pulses produced a smooth Co(Si,,,Ge,,,), film without inducing Ge segregation out of the germanosilicide and strain relaxation in the unreacted Si0.76Ge0.24 film.
Interfacial reactions of Ni/Si0.76Ge0.24 and Ni/Si1-x-yGexCy by vacuum annealing and pulsed KrF laser annealing
(2000-06-01)
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
;
電子工程學系及電子研究所
Interfacial reactions of Ni on Si0.76Ge0.24 and Si1-x-yGexCy. films by vacuum annealing and pulsed KrF laser annealing were studied by transmission electron microscopy (TEM) in conjunction with energy dispersive spectrometry (EDS) and X-ray diffraction (XRD). For the Ni/Si0.76Ge0.24 and Ni/Si1-x-yGexCy films annealed at a temperature of 200-600 degrees C Ge segregation and agglomeration occurred at an extent becoming more severe at higher temperatures. Upon pulsed KrF laser annealing the agglomeration structure was improved. The retardation of phase transformation in the Ni/Si1-x-yGexCy system was observed upon either vacuum annealing or pulsed laser annealing. Multiple-pulse annealing is an effective method to fabricate smooth Ni(Si0.76Ge0.24)(2) and Ni(Si1-x-yGexCy)(2) films without inducing Ge segregation to the remaining substrates and strain relaxation. (C) 2000 Elsevier Science B.V. All rights reserved.
Interfacial reactions of Pd/Si0.76Ge0.24 by pulsed KrF laser annealing
(1998-09-07)
Chen, DR
;
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
The interfacial reactions of Pd/Si0.76Ge0.24 were studied by pulsed KrF laser annealing as a function of energy density and pulse number. At an energy density of 0.1-0.4 J/cm(2), a continuous germanosilicide layer composed of a low-temperature phase, Pd-2(Si1-xGex), and a high-temperature phase, Pd(Si1-xGex), was formed. Incontrast to vacuum annealing, Ge segregation out of the germanosilicide layer and the strain relaxation of the residual Si0.76Ge0.24 film could be effectively suppressed by pulsed KrF laser annealing at 0.1 J/cm(2). Multiple pulse annealing at 0.1 J/cm(2) could further homogenize the Pd concentration of the germanosilicide layer and promote the growth of Pd(Si1-xGex). Concurrently, the smoothness of the germanosilicide layer was substantially improved in comparison with those grown by vacuum annealing at temperatures above 200 degrees C. The studies also revealed that for multiple pulse annealing at 0.1 J/cm(2) with a low repetition rate, 1 Hz, the evolution of phase formation and Pd diffusion could be proceeded by each individual laser pulse. (C) 1998 American Institute of Physics. [S0003-6951(98)04136-9].
Polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain
(2002-12-16)
Peng, DZ
;
Chang, TC
;
Shih, PS
;
Zan, HW
;
Huang, TY
We have fabricated a polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain (SiGe-RSD TFT). The SiGe-RSD regions were grown selectively by ultrahigh vacuum chemical vapor deposition at 550 degreesC. It was observed that, with SiH4 and GeH4 gas flow rates of 5 and 2 sccm, respectively, the poly-SiGe could be selectively grown up to 100 nm for source/drain regions. The resultant transistor structure features an ultrathin active channel region (20 nm) and a self-aligned thick source/drain region (120 nm), which is ideally suited for optimum performance. The significant improvements in electrical characteristics, such as higher turn-on current, lower leakage current, and higher drain breakdown voltage have been observed in the SiGe-RSD TFT, compared to the conventional TFT counterpart. These results indicate that TFTs with SiGe raised source/drain structure would be highly promising for ultrathin TFTs applications. (C) 2002 American Institute of Physics.
Pulsed KrF laser annealing of Mo/Si0.76Ge0.24
(2000-06-01)
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
;
Chang, TC
Interfacial reactions of Mo/Si0.76Ge0.24 were studied by pulsed KrF laser annealing as a function of the energy density and pulse number. Vacuum annealing was also performed on some samples for comparison. For the samples annealed at a temperature of 500-700 degrees C a continuous hexagonal Mo(Si1-xGex)(2) (h-Mo(Si1-xGex)(2)) film was formed, while Ge segregation from the h-Mo(Si1-xGex)(2) film to the underlying Si0.76Ge0.24 occurred with the extent becoming more severe at higher annealing temperatures. Concurrently, amorphous structures appeared in the Si0.76Ge0.24 substrate. At 700 degrees C h-Mo(Si1-xGex)(2) transformed to tetragonal Mo(Si1-xGex)(2) (t-Mo(Si1-xGex)(2)). Multiple-pulse laser annealing could produce a continuous h-Mo(Si1-xGex)(2) film without forming amorphous structures in the Si0.76Ge0.24 substrate, however, it could not suppress Ge segregation. In the present study, no t-Mo(Si1-xGex)(2) was formed upon pulsed KrF laser annealing even at higher energy densities. (C) 2000 Elsevier Science B.V. All rights reserved.
Room temperature oxidation of Cu/Si0.76Ge0.24 annealed at 200 to 300 degrees C
(1999-06-01)
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
;
電子工程學系及電子研究所
The Cu3Si-catalyzed oxidation behavior of Cu/Si0.76Ge0.24 after annealing at a temperature of 200-300 degrees C was studied using transmission electron microscopy (TEM). For the Cu/Si0.76Ge0.24 samples annealed at 200 degrees C and followed by exposure in air for 1-4 weeks an SiO2 layer embedded with precipitates containing Cu, Ge, Si, and O was formed on the surface of the Cu-3(Si1-xGex) film. During exposure the Cu atoms released from Cu-3(Si1-xGex) by oxidation diffused down to the residual Si0.76Ge0.24 film and subsequently the Si substrate to form. new Cu-3(Si1-xGex) and Cu3Si, respectively. After exposure for 5-6 weeks not only the oxidation of the surface layer became severe but also the growth of the buried SiO2 layer was initiated at the Cu-3(Si1-xGex)/Cu3Si interface. Concurrently, the Cu3Si-catalyzed oxidation of Si by inward movement of the SiO2/Si interface was also observed. As compared with the annealed Cu/Si samples the presence of Ge significantly lowered the oxidation rate of the annealed Cu/Si0.76Ge0.24 samples. Higher temperature annealing promoted the oxidation rate because of Ge segregation out of the Cu-3(Si1-xGex) layer and the formation of a larger fraction of the Cu-3(Si1-xGex)/Cu3Si interface where the buried SiO2 layer was initially formed. (C) 1999 Elsevier Science S.A. All rights reserved.